Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 66 Initial setting of Dual D1 interface
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
50
LLC_A
31
RW Line Locked Clock control for D1_A:
0: LLC_A set to input
1: LLC_A set to output, taken from LLC_B
SIO_A 30 to 29 RW Synchronization port_A configuration:
00: HS_A and VS_A are input (i.e. 3-state)
01: HS_A is output, HGT of HPS; VS_A is output, VGT of HPS
10: HS_A is output, RESET signal for a field memory VS_A is input, vertical
sync signal for BRS this setting is needed for the field memory mode
11: HS_A is output, HGT of BRS; VS_A is output, VGT of BRS
RW Polarity of VS_A, if VS output:
0: direct from HPS or BRS, see SIO_A
1: inverted
PVO_A
PHO_A
28
27
RW Polarity of HS_A, if HS output is select by SIO_A:
0: direct from HPS or BRS, see SIO_A
1: inverted
50
SYNC_A 26 to 24 RW Sync edge selection and field detection mode internal sync signals SyncA
(Ha, Va, Fa) if:
HS, VS are input: Ha/Va/Fa derived from pins
HS, VS are output: HS/VS as select by SIO_A
000: Ha at rising edge of HS; Va at rising edge of VS; Fa = HS × VS-rising,
directly
001: Ha at rising edge of HS; Va at falling edge of VS; Fa = Hs × VS-falling,
directly
010: Ha at rising edge of HS; Va at rising edge of VS; Fa = HS × VS-falling,
forced toggle
011: Ha at rising edge of HS; Va at falling edge of VS; Fa = HS × VS-falling,
forced toggle
100: Ha at rising edge of HS; Va at rising edge of VS; Fa = free toggle
101: Ha at rising edge of HS; Va at falling edge of VS; Fa = free toggle
110: Ha at rising edge of HS; Va at rising and falling edge of Frame Sync at
the VS pin; Fa = direct FS
111: Ha, Va, Fa; derived from SAV and EAV decoded from the data-stream
at D1_A port. Not used if the MSB of HPSdatasel in Table 71 is set to logic 1
50
FIDESA 23 and
22
RW Field identification port_A edge select (ODD is defined by FID = 1, EVEN is
defined by FID = 0)
00: no interrupt condition
01: rising edge is interrupt condition
10: falling edge is interrupt condition
11: both edges are interrupt condition
−
21 to 16
−
reserved
1998 Apr 09
84
NXP [ NXP ]
