Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
handbook, full pagewidth
LLC
PXQ_x
D1_x (7 to 0)
FFH
00H
00H
SAV
Cb
Y
Cr
PXQ_x
D1_x (7 to 0)
Y
Cr
Y
FFH
00H
00H
EAV
MHB052
Fig.11 Timing of PXQ_x for CCIR 656 at the D1_x port.
Table 51 Video timing reference codes
BIT NUMBER
BYTE
7 (MSB)
6
5
4
3
2
1
0 (LSB)
First
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
0
Second
Third
0
F(1)
0
V(2)
0
H(3)
0
(4)
(4)
(4)
(4)
Fourth
P3
P2
P1
P0
Notes
1. F = logic 0 during field 1 and logic 1 during field 2.
2. V = logic 0 elsewhere and logic 1 during field blanking.
3. H = logic 0 in SAV and logic 1 in EAV.
4. P0, P1, P2 and P3: protection bits (see Table 52).
Bits P0, P1, P2 and P3, have states dependent on the states of the bits F, V and H as shown in Table 52. At the receiver
(SAA7146A) this arrangement permits one-bit errors to be corrected. If two-bit errors or up to four-bit errors occur, i. e.
depending on uncoded protection bits, the circuit processes direct on the coded values. In this case the protection bits
are ignored.
SAV and EAV are only decoded and removed from the signal stream (substituted with neighbouring first or last active
video sample), if chosen this way. However, ‘single’ qualified codes of ‘00’ and/or ‘FF’ in the data stream, remain in the
data stream and are processed as data.
1998 Apr 09
59
NXP [ NXP ]
