Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 11 Main control register 2
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
Mask word
100
M15 to M00
31 to 16
RW
16-bit mask word for bit-selective writes to the control word; when
read this bits always returns logic 0
Control word
100
RPS_SIG4
15
14
13
12
11
10
RW
RW
RW
RW
RW
RW
RPS Signal 4
RPS Signal 3
RPS Signal 2
RPS Signal 1
RPS Signal 0
RPS_SIG3
RPS_SIG2
RPS_SIG1
RPS_SIG0
UPLD_D1_B
Upload ‘Video DATA stream handling at port D1_B (54H)’; see
Table 68. To upload ‘Initial setting of Dual D1 Interface (50H)’, this
bit and bit 9 must be set; see Table 66.
UPLD_D1_A
9
RW
Upload ‘Video DATA stream handling at port D1_A (54H)’; see
Table 67. To upload ‘Initial setting of Dual D1 Interface (50H)’, this
bit and bit 10 must be set; see Table 66.
UPLD_BRS
−
8
7
6
RW
−
Upload ‘BRS Control Register (58H)’; see Table 69.
Reserved; when read this bit always returns a logic 0.
Upload ‘HPS Horizontal prescale (68H)’; see Table 79.
Upload ‘HPS Horizontal fine-scale (6CH)’; see Table 81.
Upload ‘BCS control (70H)’; see Table 82.
UPLD_HPS_H
RW
UPLD_HPS_V
5
RW
Upload ‘HPS control (5CH)’; see Table 71.
Upload ‘HPS Vertical scale (60H)’; see Table 72.
Upload ‘HPS Vertical scale and gain (64H)’; see Table 73.
Upload ‘Chroma Key range (74H)’; see Table 86.
Upload ‘HPS Outputs and Formats (78H)’; see Table 87.
Upload ‘Clip control (78H)’; see Table 89.
UPLD_DMA3
UPLD_DMA2
UPLD_DMA1
4
3
2
RW
RW
RW
Upload ‘Video DMA3 registers’; 30H, 34H, 38H, 3CH, 40H, 44H
and 48H (20 to 16).
Upload ‘Video DMA2 registers’; 18H, 1CH, 20H, 24H, 28H, 2CH
and 48H (12 to 8).
Upload ‘Video DMA1 registers’; 00H, 04H, 08H, 0CH, 10H, 14H
and 48H (4 to 0).
UPLD_DEBI
UPLD_IIC
1
0
RW
RW
Upload ‘DEBI registers’; 88H, 7CH, 80H, 84H and 48H (28 to 26).
Upload ‘I2C-bus registers’; (8CH and 90H).
1998 Apr 09
34
NXP [ NXP ]
