Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
First entry of the data channel queue:
7.2.5
INTERNAL ARBITRATION CONTROL
• MMU
• RPS.
The SAA7146A has up to three video DMA channels, four
audio DMA channels and three other DMA channels (RPS,
MMU and DEBI) each trying to get access to the PCI-bus.
To handle this, an Internal Arbitration Control (INTAC) is
needed. INTAC controls on the one hand the PCI-bus
requests and on the other hand the order in which each
DMA channel gets access to the bus.
Second entry of the data channel queue:
• MMU
• and so on.
If INTAC detects at least one DMA channel in the queue or
an MMU or an RPS request, it signals the need for the bus
by setting the REQ# signal on the PCI-bus. If the GNT#
signal goes LOW, the SAA7146A is the owner of the bus
and makes the PCI master module working with the first
channel selected. The master module tries to transfer the
number of Dwords defined in the Burst Register. For RPS
the burst length is hardwired to four and for the MMU it is
hardwired to two Dwords. After that the master module
stops this transfer and starts a transfer using the next
channel (due to the round-robin).
The basic implementation of the internal arbitration control
is a round-robin mechanism on the top, consisting of the
RPS, the MMU and one of the eight data channels. Data
channel arbitration is performed using a ‘first come first
serve’ queue architecture, which may consist of up to eight
entries.
Each data channel reaching a certain filling level of its
FIFO defined by the threshold, is allowed to make an entry
into the arbitration queue. The threshold defines the
number of Dwords needed to start a sensible PCI transfer
and must be small enough to avoid a loss of data due to an
overflow regarding the PCI latency time. After each job
(Video Transfer Done, VTD) the video channels have to be
emptied and are allowed to fill an entry into the queue,
even if they have not yet reached their threshold.
If a DMA channel gets its transfer stopped due to a retry,
the arbitration control sets the corresponding retry flag.
INTAC tries to end a retried transfer, even if this transfer
gets stopped via the Transfer Enable bit (TR_E). For this
reason the Transfer Enable bits are internally shadowed
by INTAC. A transfer can only be stopped if it has no retry
pending.
Concurrently to the entry the channel sets a bit which
prohibits further entries to this channel. In the worst case,
each data channel can have only one entry in the queue.
The Arbitration Control Registers (Burst and Threshold of
DEBI, Video 1 to 3, Audio 1 to 4) are listed in Table 6.
If each channel wants to access the bus, which means the
queue is full, an order like the one shown below will be
given.
• MMU
• RPS.
1998 Apr 09
30
NXP [ NXP ]
