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Table 14 PAUSE command format
D31 TO D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0010
OAN
INV
SIG4
SIG3
SIG2
SIG1
SIG0
GPIO3
GPIO2
GPIO1
GPIO0
HT
Table 15 PAUSE command format (continued)
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HS O_FID_B E_FID_B O_FID_A E_FID_A VBI_A VBI_B BRS_DONE −
HPS_ HPS_DONE VTD3 VTD2 VTD1 DEBID IICD
LINE_
DONE
Table 16 Upload command format
D31 TO D28 D25 TO D11
0100 reserved
D10
D9
D8
D7
D6
video data stream handling video data stream handling BRS control
at Port D1_A (54H);
see Table 68
reserved horizontal-prescale (68H);
see Table 79.
at Port D1_B (54H);
see Table 67
register (58H);
see Table 69
horizontal fine-scale (6CH);
see Table 81.
BCS control (70H);
see Table 82
initial setting of Dual D1 Interface (50H)
Table 17 Upload command format (continued)
D5
D4
D3
D2
D1
D0
HPS control (5CH); see Table 71. video DMA3 (30H,
video DMA2 (18H,
video DMA1 (00H,
DEBI (88H, 7CH, 80H, IIC (8CH, 90H)
HPS vertical scale (60H);
see Table 72.
34H, 38H, 3CH,
40H, 44H, 48H);
1CH, 20H, 24H, 28H, 04H, 08H, 0CH, 10H, 84H, 48H); [28 to 26]
2CH, 48H); [12 to 8] 14H, 48H); [4 to 0]
HPS vertical scale and gain (64H); [20 to 16]
see Table 73.
Chroma key range (74H);
see Table 86.
HPS output and formats (78H);
see Table 87.
Clip control (78H); see Table 89.
NXP [ NXP ]
