Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The processing of RPS can be controlled by a sequence
of wait commands on special events. Furthermore the
program flow can be controlled via conditional jumps
related to the communication with the host setting
semaphores or special internal interrupts.
7.4
Register Programming Sequencer (RPS)
The RPS is used as an additional method to program or
read the registers of the SAA7146A. Its main function is
programming the registers on demand without delay via
the interrupt handler of the host system.
Because different applications of the SAA7146A can run
independently on and asynchronously to each other the
RPS is capable of running two parallel tasks. Both tasks
are completely equal to each other and each has its own
set of registers (RPS address, RPS page, HBI threshold
and RPS time out value). Each task can be separately
enabled by setting its related ERPSx bit in the Main control
register 1 (see Table 10). To allow communication
between both tasks and the CPU there are five signals
which can be set or reset from both tasks (see Table 11).
The programming of a task is defined by an instruction list
in the system main memory that consists of RPS
commands. The operation of the RPS is initiated on
command by setting the ERPS bit of the desired task in the
Main control register 1.
7.4.1
RESET
During a reset the ERPSx (Enable RPS of task ‘x’) bits in
the Main control register 1 (see Table 10) of the
SAA7146A are cleared so that an RPS task has to be
explicitly started.
7.4.2
EVENT DESCRIPTION
Table 12 shows the events available during the execution
of an RPS program. The execution can for example wait
on these events to become true. In general these events
are set if a rising edge of the corresponding signal occurs
and are cleared if a falling edge of the signal occurs.
If signals are logic HIGH after the reset and no rising edge
occurs the corresponding event (available in an RPS
program execution) will not be set.
Table 12 Description of events
EVENT
DESCRIPTION
IICD
IIC Done: Done flag of the I2C-bus
DEBID
DEBI Done: Done flag of DEBI; see note 1
O_FID_A; O_FID_B
E_FID_A; E_FID_B
HS
Field Identification signal: for an odd field dependent on sync detection at Port A/Port B
Field Identification signal: for an even field dependent on sync-detection at Port A/Port B
HPS Source: wait for processing of source line before line addressed by SLCT is done
HPS Target: wait for processing of target line before line addressed by TLCT is done
Vertical Blanking Indicator at Port A/Port B: for details on this signal see Table 90
Inactive BRS data path: for details on this signal see Table 90
HT
VBI_A; VBI_B
BRS_DONE
HPS_DONE
HPS_LINE_DONE
VTD1; VTD2; VTD3
Inactive HPS data path between two windows: for details on this signal see Table 90
Inactive HPS data path between two lines: for details on this signal see Table 90
Video Transfer Done: video DMA 1, video DMA 2 or video DMA 3 has transferred a complete
window and is ready to be reprogrammed
GPIO0
GPIO1
GPIO2
GPIO3
SIGx
General Purpose I/O 0: this bit reflects the status of the GPIO pin 0
General Purpose I/O 1: this bit reflects the status of the GPIO pin 1
General Purpose I/O 2: this bit reflects the status of the GPIO pin 2
General Purpose I/O 3: this bit reflects the status of the GPIO pin 3
General purpose signal x: for intertask and RPS to CPU communication or program flow
control. ‘x’ can take a value within the range 0 to 4
Note
1. If an RPS program is used to make DEBI transfer consecutive data blocks employ the following commands: LOAD
REGISTER, CLEAR SIGNAL, UPLOAD and PAUSE. Before uploading the register contents the DEBI_DONE flag
of a former transfer has to be cleared. With this, the following PAUSE command waits correctly for DEBI_DONE of
the just started DEBI block transfer.
1998 Apr 09
35
NXP [ NXP ]
