Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 6 Arbitration control registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
48
BurstDebi
Burst3
28 to 26
20 to 18
17 to 16
12 to 10
9 to 8
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PCI burst length of the DEBI DMA channel; see Table 7
PCI burst length of video Channel 3; see Table 7
threshold of FIFO 3; see Table 8
Thresh3
Burst2
PCI burst length of video Channel 2; see Table 7
threshold of FIFO 2; see Table 8
Thresh2
Burst1
4 to 2
PCI burst length of video Channel 1; see Table 7
threshold of FIFO 1; see Table 8
Thresh1
BurstA1_in
ThreshA1_in
BurstA1_out
1 and 0
28 to 26
25 to 24
20 to 18
4C
PCI burst length of audio input Channel 1; see Table 7
threshold of audio FIFO A1_in; see Table 8
PCI burst length of audio output Channel 1; see Table 7
threshold of audio FIFO A1_out; see Table 8
PCI burst length of audio input Channel 2; see Table 7
threshold of audio FIFO A2_in; see Table 8
PCI burst length of audio output Channel 2; see Table 7
threshold of audio FIFO A2_out; see Table 8
ThreshA1_out 17 and 16
BurstA2_in
12 to 10
9 and 8
4 to 2
ThreshA2_in
BurstA2_out
ThreshA2_out
1 and 0
Table 7 Burst length definition
VALUE
BURST LENGTH
000
001
010
011
100
101
110
111
1 Dword
2 Dwords
4 Dwords
8 Dwords
16 Dwords
32 Dwords
64 Dwords
128 Dwords
Table 8 Threshold definition
WRITE MODE(1)
READ MODE(1)
VALUE
VIDEO
AUDIO
VIDEO
AUDIO
00
01
10
11
4 Dwords of valid data
8 Dwords of valid data
1 Dword of valid data
4 Dwords of valid data
4 empty Dwords
8 empty Dwords
16 empty Dwords
1 empty Dword
4 empty Dwords
8 empty Dwords
16 empty Dwords
16 Dwords of valid data 8 Dwords of valid data
32 Dwords of valid data 16 Dwords of valid data 32 empty Dwords
Note
1. The threshold is reached, if the FIFO contains at least this number of Dwords.
1998 Apr 09
31
NXP [ NXP ]
