Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.4.3
COMMAND LIST
7.4.4.3
CHECK-LATE
An instruction list of an RPS task is built in the system
memory by the device driver. This list is made up of
command sequences; each command being at least one
Dword long. The first Dword of a command consists of the
instruction code (4-bit) and a command specific part
(28 bits). Commands longer than one Dword contain data
in the additional Dwords.
The CHECK_LATE command is a one Dword-command.
This command contains in the command specific part the
events to check and if necessary to wait for, as shown in
Tables 18 and 19. The execution of the RPS task is
delayed until the condition addressed via the events
becomes true, or a time out occurs and the upload is
performed.
The OAN bit specifies if the condition in bits 25 to 0 is an
AND (OAN set to 0) or if the condition is an OR (OAN set
to 1). If the INV bit is set this command will wait for the
condition to become false.
Table 13 Command Dword
D31 to D28
D27 to D0
Instruction code
command specific
If the CHECK_LATE command finds that the wait
condition is already true the RPS-LATE is set. Otherwise it
waits for the condition as the PAUSE command. A time out
behaviour such as described for the PAUSE command is
also supplied.
7.4.4
THE INSTRUCTION CODE
The instruction code identifies one of the following
commands (see bits 31 to 28 of Tables 14 to 29).
7.4.4.1
PAUSE
7.4.4.4
CLR_SIGNAL
The PAUSE command is a one Dword command. This
command contains in the command specific part the
events to wait for; see Tables 14 and 15. The execution of
the RPS task is delayed until the condition addressed via
the events becomes true or a time out occurs.
The CLR_SIGNAL Command clears the selected signals.
This will not affect the real status bits of the SAA7146A.
Only a copy of this bit related to the RPS will be cleared.
It will be set again via a SET_SIGNAL command or when
the real status will be set due to normal processing.
The CLR_SIGNAL format is shown in Tables 20 and 21.
To control the time a PAUSE command stays in the wait
state, it is possible to set a RPS time out value. This value
specifies after how many PCI clocks and/or V_syncs a
time out will be asserted. When it occurs the RPS_TO bits
in the PSR (see Table 38) is set and if enabled an interrupt
will be generated. However, the RPS will stop this task.
7.4.4.5
NOP
The NOP command consists of one Dword and has the
instruction code 0000. All bits of the command specific
part have to be set to zero. This command is a special
case of the CLR_SIGNAL command!
The OAN bit specifies if the condition in bits 25 to 0 is an
AND (OAN set to 0) or if the condition is an OR (OAN set
to 1). If the INV bit is set this command will wait for the
condition to become false.
7.4.4.6
SET_SIGNAL
The SET_SIGNAL command sets the selected signals.
If one of the SAA7146A status related signals is selected
to be set, it will not affect the real status bit of the
SAA7146A. Only a copy of this bit related to the RPS, will
be set. The SET_SIGNAL format is shown in
Tables 22 and 23.
7.4.4.2
UPLOAD
The UPLOAD command is a one Dword-command. This
command contains in the command specific part the
sections to be uploaded from the shadow RAM to the
working registers, see Tables 16 and 17.
If the UPLOAD command finds a bit of a section set it
uploads the corresponding registers from the shadow
RAM to the working registers. This is done for registers
with changed shadow RAM values only.
1998 Apr 09
36
NXP [ NXP ]
