Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 110 Status register (IICSTA); note 1
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
90
IICCC [2:0]
ABORT
SPERR
APERR
DTERR
DRERR
AL
10 to 8
RW
RW
RW
RW
RW
RW
RW
R
clock bit rate selection; see Table 111
ABORT OPERATION: clears busy bit
7
6
5
4
3
2
1
0
bus error due to invalid start/stop condition
NACK: error in address phase
NACK: error in data transmission
NACK: error when receiving data
arbitration lost
ERR
general error flag: has to be reset by clearing all error flags
operation ongoing
BUSY
R
Note
1. The error bits have to be cleared, before a new command can be executed. This may be needed twice after using
ABORT.
Table 111 Selection of I2C-bus bit rate; note 1
IICCC2
IICCC1
IICCC0
BIT RATE(2)
1
0
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
PCI clock/6400
PCI clock/3200
PCI clock/480
PCI clock/320
PCI clock/240
PCI clock/120
PCI clock/80
PCI clock/60
Notes
1. Since the maximum width of spikes suppressed by the input filter depends on the PCI clock frequency, the
appropriate timing parameter of 50 ns from the I2C-bus specification is not fulfilled. Refer to the document for further
details. This document may be ordered using the code 9398 393 40011.
2. The selected bit rate is the maximum bit rate and could be ‘stretched’ (slowed down) by slaves.
1998 Apr 09
123
NXP [ NXP ]
