Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Instead of checking the general error flag (ERR) after each
single 3-byte sequence, it is possible to check the ERR at
the end of the whole protocol sequence. During a bus
cycle, the BUSY bit is set HIGH. At the end of a bus cycle
an interrupt request is generated if enabled and BUSY is
cleared if no error occurs. Writing to the IICTRF should not
be done while the BUSY bit is active, otherwise the ERR
flag will be set HIGH. If no transfer errors occur during the
three transfer actions, the ERR bit will be set LOW. If an
error occurs the ERR bit will be set HIGH and the BUSY bit
stays HIGH. In this case the error and BUSY flags have to
be cleared before starting a new operation.
7.17.2.2 Example
The protocol sequence for reading three bytes with
subaddress access is illustrated in Fig.43. The procedure
for this read operation is detailed below:
1. Address slave, write to IICTFR (see Fig.44):
BYTE2 [7:1] = DA, BYTE2 [0] = 0 (write),
ATTR2 = START
BYTE1 = subaddress, ATTR1 = CONT
BYTE0 [7:1] = DA, BYTE0 [0] = 1(read),
ATTR0 = START
2. Wait until BUSY = 0
3. Check ERR bit, if it is inactive the slave target is
successfully addressed
4. Transfer data, write attribute information to IICTFR
(see Fig.45):
BYTE2 = first received data byte, ATTR2 = CONT
BYTE1 = second received data byte, ATTR1 = CONT
BYTE0 = third received data byte, ATTR0 = STOP
5. Wait until BUSY = 0
6. Check ERR bit, if it is inactive IICTFR contains valid
data.
handbook, full pagewidth
S
S
DA
W
A
SA
A
A
address device and transmit subaddress
DA
R
A
A
D
restart for reading from slave
receive data
D
D
NA
P
receive data
restart last byte and STOP
MGD696
Fig.43 Protocol sequence for reading three bytes with subaddress access.
1998 Apr 09
125
NXP [ NXP ]
