Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The two lists, pixel list and line list, are interlocked in the
64 Dword memory. The pixel list is located at the even
addresses, the line list at the odd addresses. This
organization reduces the number of Dwords to be loaded,
if there are less then 16 overlay windows. For example,
5 overlay windows need 20 Dwords for the coordinates
and 2 Dwords as EOF marker.
7.15 Data Expansion Bus Interface (DEBI)
7.15.1 GENERAL DESCRIPTION
The DEBI performs 16-bit parallel I/O in immediate (direct)
transfer mode and block transfer mode. The immediate
mode is used to transfer a byte, word or Dword to or from
the target device. The block transfer mode offers the
possibility to read or write up to 32 kbytes data blocks.
7.14.2.2 Driver algorithm
7.15.2 FEATURES
Overlay window coordinates are relative to the video
window and can range between 0, 0 and 2047. Relevant
coordinates are top/left, bottom + 1/right + 1 of the overlay
windows. If an overlay window has its bottom/right
coordinates at the bottom/right of the video window its
relevant coordinates bottom + 1/right + 1 would exceed
the coordinate range and therefore do not have to be
inserted into the lists.
• 8-bit and 16-bit slaves supported
• External interrupt supported, DMA suspend/resume
function
• Byte, word and Dword transfers supported
• Slaves with or without handshake ability supported due
to programmable cycle time
• Build lists: build sorted lists of lines and pixels containing
top/left, bottom + 1/right + 1 coordinates of every
overlay window, without having consecutive list entries
with the same coordinate. Every list will have an end of
list entry with all coordinate bits set to zero. This EOL
entry will follow the last entry. If there are 16 overlay
windows and no double coordinates the lists are full and
there is no last entry.
• Different endian types supported
• PCI DMA master transfer in block mode
• Optional address increment in block mode.
7.15.3 DEBI PINS
There are 21 DEBI pins. Most of the control signals
represent different functions with respect to the selected
interface mode (Intel/ISA or Motorola/68 kbytes).
• Insert display information: for every relevant coordinate
in both lists and for every overlay window, if the
coordinate in the line/pixel list is in between the
top/bottom or left/right coordinates of the overlay
window then set the display information bit to 1
(‘display’). Otherwise, set the display information bit to 0
(‘no_display’).
Table 92 DEBI pin list
PIN NAME
TYPE
DESCRIPTION
AD15 to AD0
AS_ALE
input/output
output
multiplexed address and data lines
address strobe/address latch enable
upper data strobe/write not
UDS_WRN
LDS_RDN
RWN_SBHE
DTACK_RDY
GPIO3
output
output
lower data strobe/read not
output
read/write not/system byte HIGH enable
data acknowledge/ready (should be pulled HIGH if not used)
optional external interrupt input
input
input/output
(used here as input only)
1998 Apr 09
101
NXP [ NXP ]
