Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 89 Clip control
OFFSET
NAME
BIT
TYPE
DESCRIPTION
78H
−
15 to 10
9 and 8
−
reserved
ClipCK
RW
clipping by chroma key CK (or MSB of α-8): OR-ed with other clip
list or clip-bit mask, if ClipMode is enabled
00: chroma key CK is not used for clipping, CK → α
01: chroma key CK is not used for clipping, inverted CK → α
10: clipping, based on chroma key CK bit
11: clipping, based on chroma key CK bit inverted
reserved
−
7
−
ClipMode
6 to 4
RW
clipping based on DMA2 read information: OR-ed with chroma
key CK, if ClipCK is enabled
000: no clipping based on DMA2 read, DMA2 can be used to write
decomposed format U
001: no clipping based on DMA2 read; DMA2 reads 8-bit-α to
substitute CK in α-formats
010: reserved
011: reserved
100: clipping, based on pixel clip list, rectangular overlays
101: clipping, based on pixel clip list, rectangular overlays,
inverted
110: clipping, based on pixel clip bit mask 1-bit/pixel
111: clipping, based on pixel clip bit mask 1-bit/pixel, inverted
select interlaced mode for rectangular overlays:
0: normal mode
RecInterl
3
RW
1: interlaced mode, this bit must be set if only one clip list for both
fields is available. This function assumes that the ODD field is
always above the EVEN field.
−
2
−
reserved
ClipOut
1 and 0
RW
use of DMA3 to report (write) key of clip information back:
00: no clip output, DMA3 can be used to write decomposed format
V, or to serve BRS, read or write
01: DMA3 writes chroma key information CK; 1-bit/pixel
10: DMA3 writes back (clip mask-CK); 1-bit /pixel
11: DMA3 writes applied pixel clipping back; 1-bit/pixel
new field. To avoid conflicts, e.g. change of vertical
settings during vertical processing, the MASKWRITE
7.13 Scaler event description
The RPS is controlled by the PAUSE command on special
events. This section describes the video events. Because
of these video events a defined time for an upload is given.
Table 90 shows the UPLOAD handling for the scaler
registers. For special applications it can also be useful to
select other combinations. For this the termination of the
UPLOAD must guarantee that the UPLOAD is completed
before the processing restarts, e.g. with a new line or a
command can be used to change single bits within a
Dword. Each video event can force only one upload at a
time. This means that the video event is cleared by the
circuit as described below, if the corresponding upload has
occurred.
1998 Apr 09
97
NXP [ NXP ]
