Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The overlay clipping combines the coordinates with
7.14 Clipping
display information which is a ‘overlay/no_overlay’
(1, 0) bit for each overlay window. A simple example,
shown in Fig.28, illustrates the relationship between
coordinates and display information.
The SAA7146A supports clipping in the HPS data path.
Clipping can be achieved with the chroma key information
or with clip data information coming via master read
through FIFO 2. Both sources will be OR-ed and can be
switched on/off or inverted individually. These settings are
controlled by the registers ClipCK and ClipMode.
In this example one overlay window ‘a’ (5, 1; 8, 3) is
defined. Relevant coordinates for the algorithm are the
coordinates where display information changes. At the
top/left coordinates (5, 1) the display information will be set
to 1 (‘overlay’). Therefore, first list entries are (5, 1) for the
pixel list and (1, 1) for the line list. The overlay will end at
the bottom/right coordinates plus one, e.g. at (9, 4)
(8 + 1, 3 + 1). This will lead to the list entries (9, 0) for the
pixel list and (4, 0) for the line list.
The information read via FIFO 2 can be used for clipping
with rectangular overlays or for bit mask clipping.
The overlay clipping supports up to 16 rectangular
overlays using 64 Dwords. The bit mask clipping allows an
arbitrary number of window clips of any size or shape. This
mode needs one bit for every pixel.
Chroma or clip information can be written to system
memory via FIFO 3. This is controlled by the ClipOut
register. It is possible to combine the clip information with
the inversion of the applied (foreground) chroma key.
The result is a mask leaving the (background) area free.
This mask can be read back in the next field to clip a
different video stream to be placed into the same window
as background (blue boxing).
The central element of the rectangular overlay clipping
combines the display information of lines and pixels held in
the registers PIXEL_INFO and LINE_INFO. This unit will
provide the ‘no_display’ information when both line and
pixel display information are set to ‘no_display’. In the
example shown in Fig.28, this will happen for the pixels
5 to 8 and for the lines 1 to 3.
If there is more than one overlay window, the window
display information of all windows will be combined into
one display information. If any of the display information of
any window is indicated ‘no_display’ the actual pixel will
not be displayed. This ensures that overlapping overlay
windows will be handled by the hardware, since the video
information will only be displayed when no window is lying
over it. Since the overlapping information is only implicitly
in the lists, the overlapping information need not be taken
into account during the creation of the lists.
It should be noted that planar output formats overrule the
use of FIFO 2 and FIFO 3 for clipping. Only chroma
clipping is available and no clip information can be written.
7.14.1 BIT MASK CLIPPING
The bit mask clipping will use one Dword as clip data for
32 pixels. The first bit of clip data is the MSB.
7.14.2 RECTANGULAR OVERLAY CLIPPING
The main part of the algorithm is responsible for loading
the display information registers PIXEL_INFO and
LINE_INFO. Both will be initialized to ‘display’. LINE_INFO
will be updated at the beginning of every line, when the line
counter is equal to the LINE_NR in the line list.
PIXEL_INFO will be updated when the pixel counter is
equal to the PIXEL_NR in the pixel list. If there is no new
information both registers will hold their old values.
The rectangular overlay clipping is responsible for
occluding rectangular overlay windows lying over a video
window.
The rectangular clipping algorithm needs two lists; one for
pixels and one for lines. Every list element in both lists
contains a coordinate and display information for every
overlay window. The 64 Dword FIFO 2 allows up to
16 overlay windows, each having two pixel list entries and
two line list entries.
Both line and pixel list have to be sorted from top to bottom
or left to right coordinates and are not allowed to have two
consecutive list elements with the same coordinate. In the
example shown in Fig.29, the list entry with line
coordinate 1 will hold the ‘display’ information of window
‘a’ and the ‘no_display’ information of window ‘c’, so two
list elements with the same coordinate are merged into
one. The last elements in the lists are characterized by the
coordinate 0.
The rectangular overlay clipping can be used in interlaced
or non-interlaced mode. This is controlled by the
‘RecInterl’ register bit. The overlay window coordinates are
defined for the target window, independent of whether the
video will be written interlaced or non-interlaced into the
target window.
Every overlay window is defined by its top/left and
bottom + 1/right + 1 coordinates. The coordinates are
relative to the top left (0, 0) reference of the video window.
1998 Apr 09
99
NXP [ NXP ]
