Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
Table 126 Vertical luminance phase offset ‘00’; register set A (BCH[7:0]) and B (ECH[7:0])
CONTROL BITS D7 TO D0
VERTICAL LUMINANCE PHASE
OFFSET
YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00
Offset = 0
Offset = 32
Offset = 255
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
⁄
32 = 1 line
32 lines
⁄
16 PROGRAMMING START SET-UP
16.1 Decoder part
The given values force the following behaviour of the SAA7114H decoder part:
• The analog input AI11 expects an NTSC M, PAL BDGHI or SECAM signal in CVBS format; analog anti-alias filter and
AGC active
• Automatic field detection enabled
• Standard ITU 656 output format enabled on expansion (X) port
• Contrast, brightness and saturation control in accordance with ITU standards
• Adaptive comb filter for luminance and chrominance activated
• Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.
Table 127 Decoder part start set-up values for the three main standards
SUB
ADDRESS
(HEX)
VALUES (HEX)
REGISTER
FUNCTION
BIT NAME(1)
NTSC M PAL BDGHI SECAM
00
01
chip version
ID07 to ID04
read only
horizontal increment
delay
X, X, X, X, IDEL3 to IDEL0
08
C0
10
08
C0
10
08
C0
10
02
03
analog input control 1
FUSE1 and FUSE0, GUDL1 to GUDL0,
MODE3 to MODE0
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
90
90
EB
E0
98
90
90
EB
E0
98
90
90
EB
E0
98
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
09
0A
0B
0C
luminance control
BYPS, YCOMB, LDEL, LUBW,
LUFI3 to LUFI0
40
80
44
40
40
80
44
40
1B
80
44
40
luminance brightness
control
DBRI7 to DBRI0
DCON7 to DCON0
DSAT7 to DSAT0
luminance contrast
control
chrominance saturation
control
2000 Mar 15
127
NXP [ NXP ]
