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SAA7114H 参数 Datasheet PDF下载

SAA7114H图片预览
型号: SAA7114H
PDF下载: 下载PDF文件 查看货源
内容描述: PAL / NTSC / SECAM视频解码器具有自适应PAL / NTSC梳状滤波器, VBI数据限幅器和高性能的定标器 [PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC combfilter, VBI-data slicer and high performance scaler]
分类和应用: 解码器转换器色度信号转换器消费电路商用集成电路
文件页数/大小: 140 页 / 549 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Preliminary specification  
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC  
comb filter, VBI-data slicer and high performance scaler  
SAA7114H  
15.5.12 SUBADDRESSES B0H TO BFH  
Table 122 Vertical luminance scaling increment; register set A (B0H[7:0]; B1H[7:0]) and B (E0H[7:0]; E1H[7:0])  
CONTROL BITS  
VERTICAL LUMINANCE SCALING  
INCREMENT  
A (B1H[7:4])  
B (E1H[7:4])  
A (B1H[3:0])  
B (E1H[3:0])  
A (B0H[7:4])  
B (E0H[7:4])  
A (B0H[3:0])  
B (E0H[3:0])  
YSCY[15:12]  
0000  
YSCY[11:8]  
0000  
YSCY[7:4]  
0000  
YSCY[3:0]  
0001  
Scale = 10241 (theoretical) zoom  
Scale = 1024  
Scale = 1, equals 1024  
Scale = 1024  
1025 down-scale  
Scale = 163.999 down-scale  
1023 zoom  
0000  
0011  
1111  
1111  
0000  
0100  
0000  
0000  
0000  
0100  
0000  
0001  
1111  
1111  
1111  
1111  
Table 123 Vertical chrominance scaling increment; register set A (B2H[7:0]; B3H[7:0]) and B (E2H[7:0]; E3H[7:0])  
CONTROL BITS  
VERTICAL CHROMINANCE  
SCALING INCREMENT  
A (B3H[7:4])  
B (E3H[7:4])  
A (B3H[3:0])  
B (E3H[3:0])  
A (B2H[7:4])  
B (E2H[7:4])  
A (B2H[3:0])  
B (E2H[3:0])  
YSCC[15:12]  
YSCC[11:8]  
YSCC[7:4]  
YSCC[3:0]  
This value must be set to the  
luminance value YSCY[15:0]  
0000  
1111  
0000  
1111  
0000  
1111  
0001  
1111  
Table 124 Vertical scaling mode control; register set A (B4H[4 and 0]) and B (E4H[4 and 0])  
X = don’t care.  
CONTROL BITS D4 AND D0  
VERTICAL SCALING MODE CONTROL  
YMIR  
YMODE  
Vertical scaling performs linear interpolation between lines  
X
X
0
1
Vertical scaling performs higher order accumulating interpolation, better alias  
suppression  
No mirroring  
0
1
X
X
Lines are mirrored  
Table 125 Vertical chrominance phase offset ‘00’; register set A (B8H[7:0]) and B (E8H[7:0])  
CONTROL BITS D7 TO D0  
VERTICAL CHROMINANCE PHASE  
OFFSET  
YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00  
Offset = 0  
Offset = 32  
Offset = 255  
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
32 = 1 line  
32 lines  
2000 Mar 15  
126  
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