Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
15.5.11 SUBADDRESSES A8H TO AEH
Table 118 Horizontal luminance scaling increment; register set A (A8H[7:0]; A9H[7:0]) and B (D8H[7:0]; D9H[7:0])
CONTROL BITS
HORIZONTAL LUMINANCE
SCALING INCREMENT
A(A9H[7:4])
B(D9H[7:4])
A(A9H[3:0])
B(D9H[3:0])
A(A8H[7:4])
B(D8H[7:4])
A(A8H[3:0])
B(D8H[3:0])
XSCY[15:12]
XSCY[11:8]
XSCY[7:4]
XSCY[3:0]
Scale = 1024⁄1 (theoretical) zoom
0000
0000
0000
0001
0000
0010
0000
0110
Scale = 1024
data path structure
Scale = 1024
1023 zoom
Scale = 1, equals 1024
⁄294, lower limit defined by
⁄
0000
0000
0000
0001
0011
0100
0100
1111
1111
0000
0000
1111
1111
0000
0001
1111
Scale = 1024
Scale = 1024
⁄
1025 down-scale
8191 down-scale
⁄
Table 119 Horizontal luminance phase offset; register set A (AAH[7:0]) and B (DAH[7:0])
CONTROL BITS D7 TO D0
HORIZONTAL LUMINANCE PHASE
OFFSET
XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0
Offset = 0
Offset = 1⁄32 pixel
Offset = 32
Offset = 255
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
⁄
32 = 1 pixel
32 pixel
⁄
Table 120 Horizontal chrominance scaling increment; register set A (ACH[7:0]; ADH[7:0]) and B (DCH[7:0]; DDH[7:0])
CONTROL BITS
HORIZONTAL CHROMINANCE
SCALING INCREMENT
A (ADH[7:4])
B (DDH[7:4])
A (ADH[3:0])
B (DDH[3:0])
A (ACH[7:4])
B (DCH[7:4])
A (ACH[3:0])
B (DCH[3:0])
XSCC[15:12](1)
0000
XSCC[11:8]
0000
XSCC[7:4]
0000
XSCC[3:0]
0000
This value must be set to the
luminance value 1⁄2XSCY[15:0]
0000
0000
0000
0001
0001
1111
1111
1111
Note
1. Bits XSCC[15:13] are reserved and are set to logic 0.
Table 121 Horizontal chrominance phase offset; register set A (AEH[7:0]) and B (DEH[7:0])
CONTROL BITS D7 TO D0
HORIZONTAL CHROMINANCE
PHASE OFFSET
XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0
This value must be set to 1⁄2XPHY[7:0]
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
2000 Mar 15
125
NXP [ NXP ]
