Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
16.2 Audio clock generation part
The given values force the following behaviour of the SAA7114H audio clock generation part:
• Used crystal is 24.576 MHz
• Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
• Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz
• AMCLK is externally connected to AMXCLK (short-cut between pins 37 and 41)
• ASCLK = 32 × 44.1 kHz = 1.4112 MHz
• ALRCLK is 44.1 kHz.
Table 128 Audio clock part set-up values
SUB
ADDRESS
(HEX)
START VALUES
REGISTER FUNCTION
BIT NAME(1)
ACPF7 to ACPF0
ACPF15 to ACPF8
7 6 5 4 3 2 1 0 HEX
30
31
32
audio master clock cycles per
field; bits 7 to 0
1 0 1 1 1 1 0 0 BC
audio master clock cycles per
field; bits 15 to 8
1 1 0 1 1 1 1 1 DF
audio master clock cycles per
field; bits 17 and 16
X, X, X, X, X, X, ACPF17 and ACPF16 0 0 0 0 0 0 1 0 02
33
34
reserved
X, X, X, X, X, X, X, X
ACNI7 to ACNI0
0 0 0 0 0 0 0 0 00
1 1 0 0 1 1 0 1 CD
audio master clock nominal
increment; bits 7 to 0
35
36
audio master clock nominal
increment; bits 15 to 8
ACNI15 to ACNI8
1 1 0 0 1 1 0 0 CC
0 0 1 1 1 0 1 0 3A
audio master clock nominal
increment; bits 21 to 16
X, X, ACNI21 to ACNI16
37
38
39
3A
reserved
X, X, X, X, X, X, X, X
X, X, SDIV5 to SDIV0
X, X, LRDIV5 to LRDIV0
0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 1 1 03
0 0 0 1 0 0 0 0 10
0 0 0 0 0 0 0 0 00
clock ratio AMXCLK to ASCLK
clock ratio ASCLK to ALRCLK
audio clock generator basic
set-up
X, X, X, X, APLL, AMVR, LRPH,
SCPH
3B to 3F reserved
X, X, X, X, X, X, X, X
0 0 0 0 0 0 0 0 00
Note
1. All X values must be set to LOW.
2000 Mar 15
129
NXP [ NXP ]
