Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
16.4 Scaler and interfaces
16.4.1 TRIGGER CONDITION
Table 130 shows some examples for the scaler
programming with:
For trigger condition STRC[1:0]90H[1:0] not equal ‘00’.
If the value of (YO + YS) is greater equal 262 (NTSC),
respectively 312 (PAL) the output field rate is reduced to
30 Hz, respectively 25 Hz.
• prsc = prescale ratio
• fisc = fine scale ratio
• vsc = vertical scale ratio.
Horizontal and vertical offsets (XO and YO) have to be
used to adjust the displayed video in the display window.
As this adjustment is application dependent, the listed
values are only dummy values.
number of input pixel
number of output pixel
The ratio is defined as:
----------------------------------------------------------
In the following settings the VBI-data slicer is inactive. To
activate the VBI-data slicer, VITX[1:0]86H[7:6] has to be
set to ‘11’. Dependent on the VBI-data slicer settings, the
sliced VBI-data are inserted after end of scaled video lines,
if the regions of VBI-data slicer and scaler overlaps.
16.4.2 MAXIMUM ZOOM FACTOR
The maximum zoom factor is dependent on the back-end
data rate and therefore back-end clock and data format
dependent (8 or 16-bit output). The maximum horizontal
zoom is limited to about 3.5, due to internal data path
restrictions.
To compensate the running-in of the vertical scaler, the
vertical input window lengths are extended by
2 to 290 lines, respectively 242 lines for XS, but the scaler
increment calculations are done with 288, respectively
240 lines.
16.4.3 EXAMPLES
Table 130 Example configurations
EXAMPLE
NUMBER
INPUT
WINDOW WINDOW
OUTPUT
SCALE
RATIOS
SCALER SOURCE AND REFERENCE EVENTS
1
analog input to 8-bit I-port output, with SAV/EAV codes, 8-bit
serial byte stream decoder output at X-port; acquisition trigger
at falling edge vertical and rising edge horizontal reference
signal; H and V-gates on IGPH and IGPV, IGP0 = VBI sliced
data flag, IGP1 = FIFO almost full, level ≥24, IDQ qualifier
logic 1 active
720 × 240 720 × 240 prsc = 1;
fisc = 1;
vsc = 1
2
3
4
analog input to 16-bit output, without SAV/EAV codes, Y on
I-port, UV on H-port and decoder output at X-port; acquisition
trigger at falling edge vertical and rising edge horizontal
reference signal; H and V-pulses on IGPH and IGPV, output
FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active
704 × 288 768 × 288 prsc = 1;
fisc = 0.91667;
vsc = 1
X-port input 8 bit with SAV/EAV codes, no reference signals on 720 × 240 352 × 288 prsc = 2;
XRH and XRV, XCLK as gated clock; field detection and
acquisition trigger on different events; acquisition triggers at
rising edge vertical and rising edge horizontal; I-port output
8 bit with SAV/EAV codes like example number 1
fisc = 1.022;
vsc = 0.8333
X-port and H-port for 16-bit YUV 4 : 2 : 2 input (if no 16-bit
output selected); XRH and XRV as references; field detection
and acquisition trigger at falling edge vertical and rising edge
horizontal; I-port output 8 bit with SAV/EAV codes, but Yonly
output
720 × 288 200 × 80 prsc = 2;
fisc = 1.8;
vsc = 3.6
2000 Mar 15
131
NXP [ NXP ]
