xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 25: I2C-bus receiver/transmitter overview …continued
Register function
Subaddress D7
(hex)
D6
D5
D4
D3
D2
D1
D0
[1]
[1]
AC1
40
FISET
HAM_N
LCR02_6
LCRn_6
LCR24_6
FC6
FCE
HUNT_N
LCR02_4
LCRn_4
LCR24_4
FC4
CLKSEL1
LCR02_2
LCRn_2
LCR24_2
FC2
CLKSEL0
LCR02_1
LCRn_1
LCR24_1
FC1
LCR2
41
LCR02_7
LCRn_7
LCR24_7
FC7
LCR02_5
LCRn_5
LCR24_5
FC5
LCR02_3
LCRn_3
LCR24_3
FC3
LCR02_0
LCRn_0
LCR24_0
FC0
LCR3 to LCR23
LCR24
42 to 56
57
FC
58
HOFF
59
HOFF7
VOFF7
HOFF6
HOFF5
HOFF4
VOFF4
HOFF3
HOFF2
VOFF2
HOFF1
VOFF1
HOFF0
VOFF0
VOFF
5A
VOFF6
VOFF5
VOFF3
[1]
[1]
[1]
HVOFF
For testability
Reserved
5B
FOFF
VOFF8
HOFF10
HOFF9
HOFF8
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
5C
[1]
[1]
[1]
[1]
[1]
[1]
5D
Sliced data identification code 5E
SDID
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Reserved
5F
DR (read only)
LN1 (read only)
LN2 (read only)
60
-
-
FC8V
-
FC7V
VPSV
LN8
PPV
LN7
CCV
LN6
-
-
61
F21_N
LN5
LN4
62
LN3
LN2
LN1
LN0
DT3
DT2
DT1
DT0
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Reserved for future
extensions
63 to FF
[1] All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
NXP [ NXP ]
