SAA7113H
Philips Semiconductors
9-bit video input processor
9.2.1 Subaddress 00h (read only register)
Table 26: Chip version subaddress 00h (D7 to D4)
Function
Logic levels
ID07
ID06
ID05
ID04
Chip Version (CV)
CV3
CV2
CV1
CV0
9.2.2 Subaddress 01h
Table 27: Horizontal increment delay subaddress 01h (D3 to D0)
Function
IDEL3
IDEL2
IDEL1
IDEL0
No update
1
1
1
0
1
1
0
0
1
1
0
0
1
0
0
0
Minimum delay
Recommended position
Maximum delay
The programming of the horizontal increment delay is used to match internal processing
delays to the delay of the ADC. Use recommended position only.
9.2.3 Subaddress 02h
Table 28: Analog control 1 subaddress 02h (D3 to D0)
Function[1]
Control bits D3 to D0
MODE3 MODE2 MODE1 MODE0
Mode 0: CVBS (automatic gain) from AI11 (pin 4)
Mode 1: CVBS (automatic gain) from AI12 (pin 7)
Mode 2: CVBS (automatic gain) from AI21 (pin 43)
Mode 3: CVBS (automatic gain) from AI22 (pin 1)
Mode 4: reserved
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
Mode 5: reserved
Mode 6[2]: Y (automatic gain) from AI11 (pin 4) + C (gain
adjustable via GAI28 to GAI20) from AI21 (pin 43)
Mode 7[2]: Y (automatic gain) from AI12 (pin 7) + C (gain
adjustable via GAI28 to GAI20) from AI22 (pin 1)
Mode 8[2]: Y (automatic gain) from AI11 (pin 4) + C (gain
adapted to Y gain) from AI21 (pin 43)
Mode 9[2]: Y (automatic gain) from AI12 (pin 7) + C (gain
adapted to Y gain) from AI22 (pin 1)
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
Modes 10 to 15: reserved
[1] Mode select (see Figure 27 to Figure 34).
[2] To take full advantage of the YC-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09h, bit 7) should be set to
logic 1 (full luminance bandwidth).
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
37 of 75
NXP [ NXP ]
