SAA7113H
Philips Semiconductors
9-bit video input processor
Table 22: Digital output control via RTS1 (enabled by bits RTSE1[3:0] = 0)
Bit OEYC
Pin RTS1 (DOT)
LOW
Pins VPO7 to VPO0
0
1
0
1
Z
LOW
active
HIGH
Z
Z
HIGH
9. I2C-bus description
9.1 I2C-bus format
S
ACK-s
ACK-s
ACK-s
P
SLAVE ADDRESS W
SUBADDRESS
DATA
data transferred
(n bytes + acknowledge)
mhb339
Fig 25. Write procedure
S
SLAVE ADDRESS W
SLAVE ADDRESS R
ACK-s
ACK-s
SUBADDRESS
DATA
ACK-s
Sr
ACK-m
P
data transferred
(n bytes + acknowledge)
mhb340
Fig 26. Read procedure (combined format)
Table 23: Description of I2C-bus format[1]
Code
Description
S
START condition
Sr
repeated START condition
0100 1010 (= 4Ah, default)
Slave address W
0100 1000 (= 48h, if pin RTS0 strapped to ground via a 3.3 kΩ resistor)
0100 1011 (= 4Bh, default)
Slave address R
0100 1001 (= 49h, if pin RTS0 strapped to ground via a 3.3 kΩ resistor)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte (see Table 24)
ACK-s
ACK-m
Subaddress
Data
data byte; see Table note 2
P
STOP condition
X = LSB slave address read/write control bit; X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)
[1] The SAA7113H supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbit/s).
[2] If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
33 of 75
NXP [ NXP ]
