SAA7113H
Philips Semiconductors
9-bit video input processor
Table 30: Analog control 1 subaddress 02h (D7 and D6) (see Figure 6)
Analog function select FUSE Control bits D7 and D6
FUSE1
FUSE0
Amplifier plus anti-alias filter bypassed
0
0
1
1
0
1
0
1
Amplifier active
Amplifier plus anti-alias filter active
9.2.4 Subaddress 03h
Table 31: Analog control 2 (AICO2) subaddress 03h
Function
Logic level
see Table 32
see Table 33
Data bit
D0
Static gain control channel 1 (GAI18) (see subaddress 04h)
Sign bit of gain control
Static gain control channel 2 (GAI28) (see subaddress 05h)
Sign bit of gain control
D1
Gain control fix (GAFIX)
Automatic gain controlled by MODE3 to MODE0
Gain is user programmable via GAI1 + GAI2
Automatic gain control integration (HOLDG)
AGC active
0
1
D2
D2
0
1
D3
D3
AGC integration hold (freeze)
White peak off (WPOFF)
White peak control active
0
1
D4
D4
White peak off
AGC hold during vertical blanking period (VBSL)
Short vertical blanking (AGC disabled during equalization and
serration pulses)
0
1
D5
D5
Long vertical blanking (AGC disabled from start of
pre-equalization pulses until start of active video (line 22 for
60 Hz, line 24 for 50 Hz)
HL not reference select (HLNRS)
Normal clamping if decoder is in unlocked state
Reference select if decoder is in unlocked state
0
1
D6
D6
9.2.5 Subaddress 04h
Table 32: Gain control analog (AICO3); static gain control channel 1 GAI1 subaddress 04h
(D7 to D0)
Decimal Gain
Sign
bit
Control bits D7 to D0
value
(dB)
GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10
0...
≈−3
≈0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
...117...
...511
≈6
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
39 of 75
NXP [ NXP ]
