SAA7113H
Philips Semiconductors
9-bit video input processor
AD2
AD1
AD2
AI22
AI21
CHROMA
AI22
CHROMA
AI21
LUMA
AI12
AI11
LUMA
AI12
AD1
AI11
mhb342
mhb341
Fig 27. Mode 0; CVBS (automatic gain)
Fig 28. Mode 1; CVBS (automatic gain)
AD2
AD2
AI22
AI22
CHROMA
CHROMA
AI21
AI21
LUMA
LUMA
AI12
AD1
AI11
AI12
AD1
AI11
mhb343
mhb344
Fig 29. Mode 2; CVBS (automatic gain)
Fig 30. Mode 3; CVBS (automatic gain)
AD2
AD2
AI22
CHROMA
AI22
CHROMA
AI21
AI21
LUMA
AI12
AD1
AI11
LUMA
AI12
AD1
AI11
mhb345
mhb346
I2C-bus bit BYPS (subaddress 09h, bit 7) should be
set to logic 1 (full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09h, bit 7) should be
set to logic 1 (full luminance bandwidth).
Fig 31. Mode 6; Y + C (gain channel 2 adjusted via
GAI2)
Fig 32. Mode 7; Y + C (gain channel 2 adjusted via
GAI2)
AD2
AD2
AI22
AI21
CHROMA
AI22
AI21
CHROMA
LUMA
AI12
AI11
LUMA
AI12
AI11
AD1
AD1
mhb347
mhb348
I2C-bus bit BYPS (subaddress 09h, bit 7) should be
set to logic 1 (full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09h, bit 7) should be
set to logic 1 (full luminance bandwidth).
Fig 33. Mode 8; Y + C (gain channel 2 adapted to Y
gain)
Fig 34. Mode 9; Y + C (gain channel 2 adapted to Y
gain)
Table 29: Analog control 1 subaddress 02h (D5 and D4) (see Figure 7)
Update hysteresis for 9-bit gain
Control bits D5 and D4
GUDL1
GUDL0
Off
0
0
1
1
0
1
0
1
±1 LSB
±2 LSB
±3 LSB
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
38 of 75
NXP [ NXP ]
