SAA7113H
Philips Semiconductors
9-bit video input processor
Table 21: Explanation to Table 20
Name Explanation
SAV start of active data (see Table 8 to Table 10)
SDID sliced data identification: NEP[1], EP[2], SDID5 to SDID0, freely programmable via I2C-bus
subaddress 5Eh[5:0], e.g. to be used as source identifier
DC
Dword count: NEP[1], EP[2], DC5 to DC0; DC is inserted for software compatibility reasons
to SAA7112, but does not represent any relevant information for SAA7113H applications.
DC describes the number of succeeding 32-bit words: DC = 1⁄4(C + n), where C = 2 (the
two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to
the chosen text standard. As the sliced data are transmitted nibble wise, the maximum
number of bytes transmitted (NBT) starting at IDI1 results to: NBS = (DC × 8) − 2.
DC can vary between 1 and 11, depending on the selected data type. Note that the
number of bytes actually transmitted can be less than NBT for two reasons:
1. result of DC would result to a non-integer value (DC is always rounded up)
2. standard not recognized (wrong standard or poor input signal)
IDI1
IDI2
internal data identification 1: OP[3], FID (field 1 = 0, field 2 = 1), LineNumber8 to
LineNumber3
internal data identification 2: OP[3], LineNumber2 to LineNumber0, DataType3 to
DataType0 (see Table 7)
DLNn sliced data LOW nibble, format: NEP[1], EP[2], D3 to D0, 1, 1
DLHn sliced data HIGH nibble, format: NEP [1], EP[2], D7 to D4, 1, 1
EAV
end of active data (see Table 8 to Table 10)
[1] Inverted EP (bit 7); for EP see Table note 2.
[2] Even parity (bit 6) of bits 5 to 0.
[3] Odd parity (bit 7) of bits 6 to 0.
8.11 RTCO output
The real-time control and status output signal contains serial information about the actual
system clock (increment of the HPLL), subcarrier frequency, increment and phase (via
reset) of the FSC-PLL and PAL sequence bit. The signal can be used for various
applications in external circuits, e.g. in a digital encoder to achieve clean encoding. The
SAA7113H supports RTC level 3.1 (see external document “RTC Functional Description”,
available on request).
8.12 RTS0 and RTS1 terminals
These two pins are multifunctional inputs/output controlled by I2C-bus bits RTSE0[3:0]
and RTSE1[3:0], located in subaddress 12h (see Table 50 and Table 51).
The RTS0 terminal can be strapped to ground via a 3.3 kΩ resistor to change the I2C-bus
slave address from default 4Ah/4Bh to 48h/49h (the strapping information is read only
during the reset sequence).
The RTS1 terminal can be configured as Data Output to 3-state (DOT) input by
RTSE1[3:0] = 0000 to control the VPO port (bits 7 to 0) via hardware according
to Table 22.
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
32 of 75
NXP [ NXP ]
