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Table 24 I2C-bus receiver/transmitter overview
SUB-
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Chip version (read only)
Increment delay
00
01
ID07
(1)
ID06
(1)
ID05
(1)
ID04
(1)
−
−
−
−
IDEL3
MODE3
HOLDG
GAI13
GAI23
HSB3
IDEL2
MODE2
GAFIX
GAI12
GAI22
HSB2
IDEL1
MODE1
GAI28
GAI11
IDEL0
Analog input control 1
Analog input control 2
Analog input control 3
Analog input control 4
Horizontal sync start
Horizontal sync stop
Sync control
02
FUSE1
FUSE0
HLNRS
GAI16
GAI26
HSB6
GUDL1
VBSL
GUDL0
WPOFF
GAI14
MODE0
GAI18
GAI10
GAI20
HSB0
(1)
03
04
GAI17
GAI27
HSB7
GAI15
GAI25
HSB5
05
GAI24
GAI21
HSB1
06
HSB4
07
HSS7
HSS6
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
08
AUFD
FSEL
FOET
HTC1
HTC0
HPLL
VNOI1
APER1
BRIG1
CONT1
SATN1
HUEC1
CHBW1
CGAIN1
YDEL1
VIPB
VNOI0
APER0
BRIG0
CONT0
SATN0
HUEC0
CHBW0
CGAIN0
YDEL0
COLO
RTSE00
Luminance control
Luminance brightness
Luminance contrast
Chroma saturation
Chroma hue control
Chroma control
09
BYPS
PREF
BPSS1
BRIG5
CONT5
SATN5
HUEC5
CSTD1
CGAIN5
HDEL1
GPSW0
BPSS0
BRIG4
CONT4
SATN4
HUEC4
CSTD0
CGAIN4
HDEL0
HLSEL
RTSE10
VBLB
UPTCV
BRIG2
CONT2
SATN2
HUEC2
FCTC
0A
0B
0C
0D
0E
0F
BRIG7
CONT7
SATN7
HUEC7
CDTO
ACGC
OFTS1
GPSW1
RTSE13
BRIG6
CONT6
SATN6
HUEC6
CSTD2
CGAIN6
OFTS0
CM99
BRIG3
CONT3
SATN3
HUEC3
DCCF
CGAIN3
VRLN
Chroma gain control
Format/delay control
Output control 1
CGAIN2
YDEL2
OERT
10
11
OEYC
RTSE03
Output control 2
12
RTSE12
RTSE11
RTSE02
RTSE01
(1)
(1)
(1)
Output control 3
13
ADLSB
OLDSB
FIDP
AOSL1
AOSL0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
14
V_GATE1_START
V_GATE1_STOP
V_GATE1_MSB
15
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTO1
VSTA0
VSTO0
16
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
(1)
(1)
(1)
(1)
(1)
(1)
17
VSTO8
VSTA8
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
18 to 1E
1F
Status byte (read only,
OLDSB = 0)
INTL
HLVLN
FIDT
GLIMT
GLIMB
WIPA
COPRO
RDCAP
Status byte (read only,
OLDSB = 1)
1F
INTL
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
20 to 3F
NXP [ NXP ]
