Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
P87C552
7
6
5
4
3
2
1
0
IEN1 (E8H)
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
(LSB)
(MSB)
BIT
SYMBOL FUNCTION
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
ET2
Enable Timer T2 overflow interrupt(s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator 1 interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register 1 interrupt
Enable T2 Capture register 0 interrupt
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
SU00755
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.
Figure 27. Interrupt Enable Register (IEN1)
7
–
6
5
4
3
2
1
0
IP0 (B8H)
PAD
PS1
PS0
PT1
PX1
PT0
PX0
(LSB)
(MSB)
BIT
SYMBOL FUNCTION
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
–
Unused
PAD
PS1
PS0
PT1
PX1
PT0
PX0
ADC interrupt priority level
2
SIO1 (I C) interrupt priority level
SIO0 (UART) interrupt priority level
Timer 1 interrupt priority level
External interrupt 1 priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
SU00763
Figure 28. Interrupt Priority Register (IP0)
7
–
6
5
4
3
2
1
0
IP0H (B7H)
PADH
PS1H
PS0H
PT1H
PX1H
PT0H
PX0H
(LSB)
(MSB)
BIT
SYMBOL FUNCTION
IP0H.7
IP0H.6
IP0H.5
IP0H.4
IP0H.3
IP0H.2
IP0H.1
IP0H.0
–
Unused
PADH
PS1H
PS0H
PT1H
PX1H
PT0H
PX0H
ADC interrupt priority level high
2
SIO1 (I C) interrupt priority level high
SIO0 (UART) interrupt priority level high
Timer 1 interrupt priority level high
External interrupt 1 priority level high
Timer 0 interrupt priority level high
External interrupt 0 priority level high
SU00983
Figure 29. Interrupt Priority Register High (IP0H)
29
1999 Mar 30
NXP [ NXP ]
