Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
P87C552
7
6
5
4
3
2
1
0
IP1 (F8H)
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
(LSB)
(MSB)
BIT
SYMBOL FUNCTION
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
PT2
T2 overflow interrupt(s) priority level
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
T2 comparator 2 interrupt priority level
T2 comparator 1 interrupt priority level
T2 comparator 0 interrupt priority level
T2 capture register 3 interrupt priority level
T2 capture register 2 interrupt priority level
T2 capture register 1 interrupt priority level
T2 capture register 0 interrupt priority level
SU00764
Figure 30. Interrupt Priority Register (IP1)
7
6
5
4
3
2
1
0
IP1H (F7H)
PT2H PCM2H PCM1H PCM0H PCT3H PCT2H PCT1H PCT0H
(MSB) (LSB)
BIT
SYMBOL FUNCTION
IP1H.7
IP1H.6
IP1H.5
IP1H.4
IP1H.3
IP1H.2
IP1H.1
IP1H.0
PT2H
T2 overflow interrupt(s) priority level high
PCM2H
PCM1H
PCM0H
PCT3H
PCT2H
PCT1H
PCT0H
T2 comparator 2 interrupt priority level high
T2 comparator 1 interrupt priority level high
T2 comparator 0 interrupt priority level high
T2 capture register 3 interrupt priority level high
T2 capture register 2 interrupt priority level high
T2 capture register 1 interrupt priority level high
T2 capture register 0 interrupt priority level high
SU00984
Figure 31. Interrupt Priority Register High (IP1H)
Table 3.
Interrupt Priority Structure
Table 4.
Interrupt Vector Addresses
SOURCE
NAME
PRIORITY WITHIN LEVEL
SOURCE
NAME
VECTOR ADDRESS
(highest)
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
SIO0 (UART)
X0
T0
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
External interrupt 0
SIO1 (I C)
X0
S1
ADC
T0
CT0
CM0
X1
CT1
CM1
T1
CT2
CM2
S0
CT3
T2
↑
2
X1
ADC completion
Timer 0 overflow
T2 capture 0
T2 compare 0
External interrupt 1
T2 capture 1
T2 compare 1
Timer 1 overflow
T2 capture 2
T2 compare 2
SIO0 (UART)
T1
S0
2
SIO1 (I C)
S1
T2 capture 0
T2 capture 1
T2 capture 2
T2 capture 3
ADC completion
T2 compare 0
T2 compare 1
T2 compare 2
T2 overflow
CT0
CT1
CT2
CT3
ADC
CM0
CM1
CM2
T2
T2 capture 3
Timer T2 overflow
↓
(lowest)
30
1999 Mar 30
NXP [ NXP ]
