Philips Semiconductors
ISP1581
USB 2.0 HS interface device
and USB 1.1, supporting both the high-speed and full-speed physical layer. After
automatic speed detection, the Philips Serial Interface Engine sets the transceiver to
use either high-speed or full-speed signaling.
7.2 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC
checking/generation, Packet IDentifier (PID) verification/generation, address
recognition, handshake evaluation/generation.
7.3 Voltage regulators
Two 5 V to 3.3 V voltage regulators are integrated on-chip to separately supply the
analog transceiver and the internal logic. The analog supply voltage is available at pin
V
reg(3.3)
to supply an external 1.5 kΩ pull-up resistor on the D+ line.
Remark:
Pin V
reg(3.3)
cannot be used to supply external devices.
7.4 Memory Management Unit (MMU) and integrated RAM
The MMU and the integrated RAM provide the conversion between the USB speed
(full speed: 12 Mbit/s, high speed: 480 Mbit/s) and the Microcontroller Handler or the
DMA Handler. The data from the USB Bus is stored in the integrated RAM, which is
cleared only when the microcontroller clears the endpoint buffer or when the DMA
Handler has read/written all data from/to the endpoint buffer. A total of 8 kbytes RAM
is available for buffering.
7.5 SoftConnect
The connection to the USB is established by pulling the D+ line (for high-speed
devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1581 an external 1.5 kΩ
pull-up resistor must be connected between pins RPU and V
reg(3.3)
. The RPU pin
connects the pull-up resistor to the D+ line, when bit SOFTCT in the Mode register is
set (see
Table 7).
After a hardware reset the pull-up resistor is disconnected by
default (SOFTCT = 0). Bit SOFTCT remains unchanged by a USB bus reset.
7.6 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using 4× over-sampling principle. It is able to track the jitter and the frequency drift as
specified by the USB specification.
7.7 Multiplying PLL oscillator
A 12 MHz to 480 MHz clock multiplier Phase-Locked Loop (PLL) is integrated
on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI.
No external components are needed for the operation of the PLL.
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
9 of 73
PHILIPS [ NXP SEMICONDUCTORS ]
