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ISP1581BD 参数 Datasheet PDF下载

ISP1581BD图片预览
型号: ISP1581BD
PDF下载: 下载PDF文件 查看货源
内容描述: 通用串行总线2.0高速接口设备 [Universal Serial Bus 2.0 high-speed interface device]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输时钟
文件页数/大小: 73 页 / 1657 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Table 4:
Name
Register summary
…continued
Destination
Address
(Hex)
30
34
38 (byte 0)
39 (byte 1)
Description
Size
(bytes)
1
4
DMA registers
DMA Command
DMA Transfer Counter
DMA Configuration
DMA controller
DMA controller
DMA controller
controls all DMA transfers
sets byte count for DMA Transfer
sets GDMA configuration (counter enable, 1
burst length, data strobing, bus width)
sets ATA configuration (IORDY enable,
mode selection: ATA/UDMA/MDMA/PIO)
1
DMA Hardware
1F0 Task File
1F1Task File
1F2 Task File
1F3 Task File
1F4 Task File
1F5 Task File
1F6 Task File
1F7 Task File
3F6 Task File
3F7 Task File
DMA Interrupt Reason
DMA Interrupt Enable
DMA Endpoint
DMA Strobe Timing
General registers
Interrupt
Chip ID
Frame Number
Scratch
Unlock Device
Test Mode
DMA controller
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
DMA controller
DMA controller
DMA controller
DMA controller
device
device
device
device
device
PHY
3C
40
48
49
4A
4B
4C
4D
44
4E
4F
50 (byte 0)
51 (byte 1)
54 (byte 0)
55 (byte 1)
58
60
18
70
74
78
7C
84
endian type, master/slave selection, signal 1
polarity for DACK, DREQ, DIOW, DIOR
single address word register: byte 0 (lower 2
byte) is accessed first
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access (write only; reading
returns 00H)
IDE device access
IDE device access
shows reason (source) for DMA interrupt
enables DMA interrupt sources
selects endpoint FIFO, data flow direction
strobe duration in UDMA/MDMA mode
shows interrupt sources
product ID code and hardware version
last successfully received Start Of Frame:
lower byte (byte 0) is accessed first
allows save/restore of firmware status
during ‘suspend’
direct setting of D+, D− states, loopback
mode, internal transceiver test (PHY)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
3
2
2
re-enables register access after ‘suspend’ 2
1
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
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