Philips Semiconductors
ISP1581
USB 2.0 HS interface device
8. Modes of operation
The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at
power-up:
•
Split Bus mode (BUS_CONF = 0):
8-bit multiplexed address/data bus and
separate 8-bit/16-bit DMA bus
•
Generic Processor mode (BUS_CONF = 1);
separate 8-bit address and 16-bit
data bus
Details of the bus configurations for each mode are given in
Table 3.
Typical interface
circuits for each mode are given in
Section 13 “Application information”.
Table 3:
Bus configuration modes
PIO width
AD[7:0]
A[7:0]
D[15:0]
DMA width
DMAWD = 0 DMAWD = 1
0
1
D[7:0]
D[7:0]
D[15:0]
D[15:0]
Split Bus mode:
multiplexed address/data on pins AD[7:0];
separate 8/16-bit DMA bus on pins DATA[15:0]
Generic Processor mode:
separate 8-bit address on pins
AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0]
Description
BUS_CONF
9. Register descriptions
Table 4:
Name
Initialization registers
Address
Mode
Interrupt Configuration
Interrupt Enable
DMA Configuration
DMA Hardware
Data flow registers
Endpoint Index
Control Function
Data Port
Buffer Length
Endpoint MaxPacketSize
Endpoint Type
Short Packet
endpoints
endpoint
endpoint
endpoint
endpoint
endpoint
endpoint
2C
28
20
1C
04
08
24
endpoint selection, data flow direction
endpoint buffer management
data access to endpoint FIFO
packet size counter
maximum packet size
selects endpoint type: control,
isochronous, bulk or interrupt
short packet received on OUT endpoint
1
1
2
2
2
2
2
device
device
device
device
DMA controller
DMA controller
00
0C
10
14
38
3C
USB device address + enable
power-down options, global interrupt
enable, SoftConnect
interrupt sources, trigger mode, output
polarity
interrupt source enabling
see
DMA registers
see
DMA registers
1
1
1
4
2
1
Register summary
Destination
Address
(Hex)
Description
Size
(bytes)
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
11 of 73
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