Philips Semiconductors
ISP1581
USB 2.0 HS interface device
6.2 Pin description
Table 2:
Symbol
[1]
DGND
V
CC(5.0)
AGND
V
reg(3.3)
Pin description for LQFP64
Pin
1
2
3
5
Type
[2]
-
-
-
-
Description
digital ground
supply voltage (3.3 or 5.0 V)
analog ground
regulated supply voltage (3.3 V
±
10%) from internal
regulator; supplies internal analog circuits; used to connect
decoupling capacitor and 1.5 kΩ pull-up resistor on D+ line
Remark:
Cannot be used to supply external devices.
D−
D+
RPU
RREF
MODE1
5
6
7
8
9
AI/O
AI/O
AI
AI
I
USB D− connection (analog)
USB D+ connection (analog)
connection for external pull-up resistor for USB D+ line;
must be connected to V
reg(3.3)
via a 1.5 kΩ resistor
connection for external bias resistor; must be connected to
ground via a 12.2 kΩ (± 0.1%) resistor
selects function of pin ALE/A0 (in Split Bus mode only):
0 —
ALE function (address latch enable)
1 —
A0 function (address/data indicator).
Remark:
Connect to V
CC(5.0)
in Generic Processor mode.
RESET
10
I
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset; connect to V
CC
for power-on reset
(internal POR circuit)
End Of Transfer input (programmable polarity, see
Table 37);
used in DMA slave mode only
DMA request (programmable polarity); direction depends
master: input, DMA slave: output); see
Table 37
DMA acknowledge (programmable polarity); direction of
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
interrupt request input from ATA/ATAPI peripheral
chip select output for ATAPI device
chip select output for ATAPI device
during power-up:
input to select the bus configuration
0 —
Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate 8/16-bit DMA data bus on DATA[15:0]
1 —
Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit DMA data bus on DATA[15:0].
normal operation:
address output to select the task file
register of an ATAPI device
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
EOT
DREQ
11
12
I
I/O
DACK
13
I/O
DIOR
14
I/O
DIOW
15
I/O
INTRQ
CS1
CS0
BUS_CONF/
DA0
16
17
18
19
I
O
O
I/O
Objective specification
Rev. 02 — 23 October 2000
5 of 73
PHILIPS [ NXP SEMICONDUCTORS ]
