Philips Semiconductors
ISP1581
USB 2.0 HS interface device
The ISP1581 has a fast general-purpose interface for communication with most types
of microcontrollers/processors. This Microcontroller Interface is configured by pins
BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus
configurations are available, selected via input BUS_CONF during power-up:
•
Generic Processor mode (BUS_CONF = 1):
–
AD[7:0]: 8-bit address bus (selects target register)
–
DATA[15:0]: 16-bit data bus (shared by processor and DMA)
–
Control signals: R/W and DS or RD and WR (selected via pin MODE0)
–
DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus,
DIOR and DIOW as dedicated read and write strobes.
•
Split Bus mode (BUS_CONF = 0):
–
AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data)
–
DATA[15:0]: 16-bit DMA data bus
–
Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD
and WR (selected via pin MODE0)
–
DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read
and write strobes.
For high-bandwidth data transfer, the integrated DMA handler can be invoked to
transfer data to/from external memory or devices. The DMA Interface can be
configured by writing to the proper DMA registers (see
Section 9.4).
The ISP1581 supports high-speed USB 2.0 and full-speed USB 1.1 signaling.
Detection of the USB signaling speed is done automatically.
ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled
USB endpoints.
There are 14 configurable data endpoints and 2 control endpoints. Any of the 14 data
endpoints can be separately enabled or disabled. The endpoint type (interrupt,
isochronous or bulk) and packet size of these endpoints can be individually
configured depending on the requirements of the application. Optional double
buffering increases the data throughput of the data endpoints.
The ISP1581 requires a single supply of 3.0 V or 5.0 V, depending on the I/O voltage.
It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the
analog transceiver. It supports bus-powered operation with a ‘suspend’ current below
500
µA.
The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40× PLL clock
multiplier generates the internal sampling clock of 480 MHz.
7.1 USB 2.0 transceiver
The analog transceiver interfaces directly to the USB cable via integrated termination
resistors. The high-speed transceiver requires an external resistor (12.2 kΩ
±
0.1%)
between pin RREF and ground to ensure an accurate current mirror. A full-speed
transceiver is integrated as well. This makes the ISP1581 compliant with USB 2.0
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
8 of 73
PHILIPS [ NXP SEMICONDUCTORS ]
