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ISP1581BD 参数 Datasheet PDF下载

ISP1581BD图片预览
型号: ISP1581BD
PDF下载: 下载PDF文件 查看货源
内容描述: 通用串行总线2.0高速接口设备 [Universal Serial Bus 2.0 high-speed interface device]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输时钟
文件页数/大小: 73 页 / 1657 K
品牌: NXP [ NXP ]
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ISP1581  
USB 2.0 HS interface device  
Philips Semiconductors  
9.2.2 Mode register (address: 0CH)  
This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the  
upper byte is ignored.  
The Mode register controls the resume, suspend and wake-up behaviour, interrupt  
activity, soft reset, clock signals and SoftConnect operation. This register also  
controls the Power Off mode during ‘suspend’ state.  
Table 7: Mode register: bit allocation  
Bit  
7
6
5
4
3
2
1
PWROFF  
0
0
SOFTCT  
0
Symbol  
Reset  
CLKAON SNDRSU  
GOSUSP  
SFRESET GLINTENA WKUPCS  
0
0
0
0
0
0
0
0
0
0
0
Bus reset  
Access  
unchanged  
R/W  
unchanged unchanged  
R/W R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 8: Mode register: bit description  
Bit  
Symbol  
Description  
7
CLKAON  
Clock Always On: A logic 1 indicates that the internal clocks  
are always running even during ‘suspend’ state. A logic 0  
switches off the internal oscillator and PLL, when they are not  
needed. During ‘suspend’ state, this bit must be set to logic 0 to  
meet the suspend current requirements. The clock is stopped  
after a delay of approximately 2 ms, following the setting of bit  
GOSUSP.  
6
SNDRSU  
Send Resume: Writing a logic 1 followed by a logic 0 will  
generate an upstream ‘resume’ signal of 10 ms duration, after a  
5 ms delay.  
5
4
GOSUSP  
SFRESET  
Go Suspend: Writing a logic 1 followed by a logic 0 will activate  
‘suspend’ mode.  
Soft Reset: Writing a logic 1 followed by a logic 0 will enable a  
software-initiated reset to ISP1581. A soft reset is similar to a  
hardware-initiated reset (via the RESET pin).  
3
GLINTENA  
Global Interrupt Enable: A logic 1 enables all interrupts.  
Individual interrupts can be masked OFF by clearing the  
corresponding bits in the Interrupt Enable register. Bus reset  
value: unchanged.  
2
1
WKUPCS  
PWROFF  
Wake-up on Chip Select: A logic 1 enables remote wake-up  
via a LOW level on input CS.  
Power Off mode: A logic 1 enables powering-off during  
‘suspend’ state. Output SUSPEND is configured as a power  
switch control signal for external devices (HIGH during  
‘suspend’). Bus reset value: unchanged.  
0
SOFTCT  
SoftConnect: A logic 1 enables the connection of the 1.5 kΩ  
pull-up resistor on pin RPU to the D+ line. Bus reset value:  
unchanged.  
9397 750 07648  
© Philips Electronics N.V. 2000. All rights reserved.  
Objective specification  
Rev. 02 — 23 October 2000  
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