ISP1581
USB 2.0 HS interface device
Philips Semiconductors
9.2.4 Interrupt Enable register (address: 14H)
This register enables/disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’
representing the endpoint number). All interrupts can be globally disabled via bit
GLINTENA in the Mode Register (see Table 7).
An interrupt is generated when the USB SIE receives or generates an ACK, NAK or
STALL on the USB bus. The interrupt generation depends on the Debug mode
settings of bit fields CDBGMOD, DDBGMODIN and DDBGMODOUT.
All data IN transactions use the Transmit buffers (TX), which are handled by the
DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which
are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,
OUT and SETUP) are handled by the CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, Setup and High Speed Status) can also be controlled individually. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in
Table 12.
Table 12: Interrupt Enable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
reserved
reserved
reserved
reserved
reserved
reserved
IEP7TX
IEP7RX
0
0
0
0
0
0
0
0
Bus Reset
Access
Bit
0
0
0
0
0
0
0
R/W
17
0
R/W
16
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
Symbol
Reset
IEP6TX
IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX
IEP3TX
0
IEP3RX
0
0
0
0
0
0
0
Bus Reset
Access
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9
R/W
8
15
14
13
12
11
10
Symbol
Reset
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
reserved IEP0SETUP
0
0
0
0
0
0
0
0
0
Bus Reset
Access
Bit
0
0
R/W
6
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
7
5
4
3
2
0
Symbol
Reset
reserved
IEDMA
0
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
0
IEBRST
0
0
0
0
0
0
0
0
0
0
0
Bus Reset
Access
0
0
unchanged
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 02 — 23 October 2000
16 of 73
NXP [ NXP ]
