ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
t
d7
DREQ (drive)
(1)
DACK (host)
LOW
t
d7
DIOW (host)
IORDY
t
d8
t
d9
DIOR
[
]
DATA 15:0
MGT510
(1) Programmable polarity: shown as active LOW.
Fig 33. UDMA timing: receiver pausing a burst.
DREQ (drive)
t
d3
(1)
DACK (host)
t
t
d2
h3
DIOW (host)
t
t
h3
d2
DIOR (host)
t
t
d2
t
d12
d10
IORDY (drive)
t
t
h1
t
su1
d4
[
]
CRC
t
DATA 15:0 (drive)
t
d5
h3
[
]
[
]
DA 2:0 and CS 1:0
MGT511
(1) Programmable polarity: shown as active LOW.
Fig 34. UDMA timing: drive terminating a burst during a read command.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
68 of 79