ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
DREQ (drive)
t
h3
(1)
DACK (host)
t
t
t
t
d2
d2
d3
d3
DIOW (host)
t
t
d10
d7
IORDY (drive)
t
t
d9
h3
DIOR (host)
t
t
h1
su1
CRC
[
]
DATA 15:0 (host)
t
h3
[
]
[
]
DA 2:0 and CS 1:0
MGT512
(1) Programmable polarity: shown as active LOW.
Fig 35. UDMA timing: drive terminating a burst during a write command.
t
d2
DREQ (drive)
t
d3
t
(1)
d5
DACK (host)
t
t
t
h3
h3
d4
t
d7
DIOW (host)
DIOR (host)
t
t
d3
d2
t
t
d9
d10
IORDY (drive)
t
t
h1
su1
CRC
[
]
DATA 15:0 (drive)
t
h3
[
]
[
]
DA 2:0 and CS 1:0
MGT513
(1) Programmable polarity: shown as active LOW.
Fig 36. UDMA timing: host terminating a burst during a read command.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
69 of 79
NXP [ NXP ]
