ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
t
d2
DREQ (drive)
t
t
d3
d2
(1)
DACK (host)
t
h3
DIOW (host)
t
t
d2
d10
IORDY (drive)
t
d12
t
h3
DIOR (host)
t
t
su1
CRC
h1
[
]
DATA 15:0 (host)
t
h3
[
]
[
]
DA 2:0 and CS 1:0
MGT514
(1) Programmable polarity: shown as active LOW.
Fig 37. UDMA timing: host terminating a burst during a write command.
Table 80: UDMA mode timing parameters
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Parameter
Mode 0
Mode 1
Mode 2
Min Max
Unit
Min
Max
Min
Max
Tcy1
read/write cycle time (from strobe edge
to strobe edge)
114
-
75
-
55
-
ns
tsu2
th2
tsu1
th1
td1
td2
td3
td4
td5
data set-up time at receiver
data hold time at receiver
15
5
-
10
5
-
7
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
data set-up time at sender
70
6
-
48
6
-
34
6
-
data hold time at sender
unlimited interlock time[1]
limited interlock time[1]
limited interlock time with minimum[1]
data line drivers switch-off delay
data line drivers switch-on delay (host)
data line drivers switch-on delay (drive)
-
-
-
0
-
0
-
0
-
0
150
0
150
0
150
20
-
-
10
-
20
-
-
10
-
20
-
-
10
-
20
0
20
0
20
0
-
-
-
tsu3
control signal set-up time before DACK
on
20
-
20
-
20
-
th3
td6
td7
td8
control signal hold time after DACK off
DACK on to control signal transition delay
ready to paused delay
20
20
160
-
-
20
20
125
-
-
20
20
100
-
-
ns
ns
ns
ns
70
-
70
-
70
-
strobe to ready delay to ensure a
synchronous pause
50
30
20
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
70 of 79
NXP [ NXP ]
