ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
(2)
DREQ
t
t
t
t
h1
su1
w1
w2
(1)
(1)
DACK
t
T
t
d1
cy1
d2
HIGH
DIOR/DIOW
t
h2
[
]
]
(read) DATA 15:0
t
t
su2
h3
[
(write) DATA 15:0
MGT505
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 26. GDMA slave mode timing (BURST > 01H, MODE = 02H).
(1)
DIOR/DIOW
36 ns (min)
(1)
EOT
DREQ
t
h1
004aaa012
(1) Programmable polarity: shown as active LOW.
Note: EOT should be valid for 36 ns (minimum) when DIOR/DIOW is active.
Fig 27. EOT timing in Split Bus mode.
RD/WR
36 ns (min)
(1)
EOT
DREQ
t
h1
004aaa013
(1) Programmable polarity: shown as active LOW.
Note: EOT should be valid for 36 ns (minimum) when RD/WR is active.
Fig 28. EOT timing in Generic Processor mode.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
64 of 79
NXP [ NXP ]
