ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 78: GDMA slave mode timing parameters
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Tcy1
tsu1
td1
Parameter
Min
78
10
33.33
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
read/write cycle time
-
DREQ set-up time before first DACK on
DREQ on delay after last strobe off
DREQ hold time after last strobe on
DIOR/DIOW pulse width
-
-
th1
53
tw1
39
36
-
600
tw2
DIOR/DIOW recovery time
-
td2
read data valid delay after strobe on
read data hold time after strobe off
write data hold time after strobe off
write data set-up time before strobe off
20
5
-
th2
-
th3
1
tsu2
tsu3
10
0
-
DACK setup time before DIOR/DIOW
assertion
-
ta1
DACK de-assertion after DIOR/DIOW
de-assertion
0
30
ns
14.2.3 MDMA mode
(2)
DREQ
DACK
T
cy1
(1)
(1)
t
t
t
t
t
su1
w1
w2
h1
d2
DIOR/DIOW
t
d3
t
d1
[
]
]
(write) DATA 15:0
t
h3
t
t
su2
h2
[
(read) DATA 15:0
MGT506
t
su2
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 29. MDMA master mode timing.
Table 79: MDMA mode timing parameters
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Tcy1(min)
tw1(min)
Parameter
Mode 0 Mode 1 Mode 2 Unit
read/write cycle time (minimum)[1]
DIOR/DIOW pulse width (minimum)[1]
480
215
150
150
80
120
70
ns
ns
ns
td1(max)
data valid delay after DIOR on
(maximum)
60
50
th3(min)
data hold time after DIOR off (minimum)
5
5
5
ns
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
65 of 79
NXP [ NXP ]
