ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 80: UDMA mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Parameter
Mode 0
Min
Mode 1
Min
Mode 2
Min
Unit
Max
75
20
-
Max
60
20
-
Max
50
20
-
td9
ready to final strobe edge delay
DACK off to IORDY high-Z delay
DACK on to IORDY HIGH delay
-
-
-
-
-
-
ns
ns
ns
ns
td10
td11
td12
0
0
0
final strobe edge to DREQ off or DIOW
on delay
50
-
50
-
50
-
td13
first strobe delay after control signal on
0
230
0
200
0
170
ns
[1] Interlock time is the time allowed between an action by one agent and the following action by the other agent. An agent can be a sender
or a receiver. Interlocking actions require a response signal from the other agent before processing can continue.
15. Application information
ISP1581
address
8
AD7 to AD0
data 16
DATA15 to DATA0
CPU
read strobe
write strobe
chip select
(R/W)/RD
DS/WR
CS
MGT515
Fig 38. Typical interface connections for Generic Processor mode.
[
]
DATA 15:0
DREQ
DACK
DIOW
DIOR
DMA
ISP1581
AD7 to
AD0
ALE/A0
address
INT
(R/W)/RD DS/WR
address/data
read
write
latch
enable
interrupt
strobe
strobe
8
ALE
P0.7/AD7
to
P0.0/AD0
INTn
RD
WR
8051
MICROCONTROLLER
MGT516
Fig 39. Typical interface connections for Split Bus mode (slave mode).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
71 of 79
NXP [ NXP ]
