ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
DREQ (drive)
t
d1
(1)
DACK (host)
t
t
t
t
t
su3
su3
d6
d6
d13
DIOW (host)
t
d13
DIOR (host)
t
d11
t
IORDY (drive)
t
t
t
h1
d5
d4
su1
[
]
DATA 15:0 (drive)
t
su3
[
]
[
]
DA 2:0 and CS 1:0
MGT508
(1) Programmable polarity: shown as active LOW.
Fig 31. UDMA timing: drive initiating a burst for a read command.
DREQ (drive)
t
d1
(1)
DACK (host)
t
t
d6
su3
DIOW (host)
IORDY (drive)
DIOR (host)
t
t
d2
d11
t
t
d1
su3
t
t
h1
su1
[
]
DATA 15:0 (host)
t
su3
[
]
[
]
DA 2:0 and CS 1:0
MGT509
(1) Programmable polarity: shown as active LOW.
Fig 32. UDMA timing: drive initiating a burst for a write command.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
67 of 79
NXP [ NXP ]
