ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 2:
Symbol[1]
Pin description…continued
Pin Ball
LQFP64 TFBGA64
Type[2] Description
VCC
D12
14
J2
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
15
16
17
18
J1
I/O
bit 12 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
D13
D14
D15
K1
K2
J3
I/O
I/O
I/O
bit 13 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 14 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 15 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
digital ground
DGND
RD
19
20
K3
J4
-
I
read strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a read to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
CS
21
22
K4
J5
I
I
chip select input (active LOW); enables the HC/DC driver to access
the buffer memory and registers of the HC/DC
input
WR
write strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a write to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
TEST0
23
24
K5
J6
I/O
O
for test input and output; pulled HIGH by a 100 kΩ resistor
bidirectional, push-pull input, three-state output
DREQ1
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the HC; the active level (HIGH or LOW)
of the request is programmed by using the HcHardwareConfiguration
register (20H/A0H)
If the OneDMA bit of the HcHardwareConfiguration register is set to
logic 1, both the HC and DC DMA channel will be routed to DREQ1
and DACK1.
push-pull output
DREQ2
25
K6
O
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the DC; the active level (HIGH or LOW)
of the request is programmed by using the DcHardwareConfiguration
register (BAH/BBH)
push-pull output
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
9 of 150
NXP [ NXP ]
