Philips Semiconductors
ISP1362
Single-chip USB OTG controller
7. Pinning information
7.1 Pinning
49 OTG_DM1
48 ID
47 H_DP2
46 H_DM2
45 OTGMODE
44 X2
43 X1
42 H_OC1
41 H_OC2
40 VCC
39 GL
38 CLKOUT
37 DGND
36 H_PSW2
35 H_PSW1
34 D_SUSPEND/D_WAKEUP
33 H_SUSPEND/H_WAKEUP
D14 17
D15 18
DGND 19
RD 20
CS 21
WR 22
TEST0 23
DREQ1 24
DREQ2 25
VCC 26
DGND 27
DACK1 28
DACK2 29
INT1 30
INT2 31
RESET 32
004aaa050
DGND 1
D2 2
D3 3
VCC 4
D4 5
D5 6
D6 7
D7 8
ISP1362BD
DGND 9
D8 10
D9 11
D10 12
D11 13
VCC 14
D12 15
D13 16
Fig 2. Pin configuration LQFP64.
50 OTG_DP1
54 CP_CAP2
53 CP_CAP1
56 VDD_5V
60 TEST2
59 TEST1
57 DGND
51 AGND
55 VBUS
58 VCC
52 VCC
64 D1
63 D0
62 A1
61 A0
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
6 of 150
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