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12 MHz
CLKOUT
X2
X1
43
44
38
32
33
internal
reset
POWER-ON
RESET
HC BUFFER
MEMORY
RESET
PLL
ISP1362
H_SUSPEND/
H_WAKEUP
to system
clock
2, 3,
5 to 8,
56
35
36
42
41
V
DD_5V
10 to 13,
15 to 18,
63, 64
ADVANCED PHILIPS
SLAVE HOST
CONTROLLER
H_PSW1
H_PSW2
H_OC1
OVERCURRENT
PROTECTION
16
D0 to D15
H_OC2
20
21
22
61
62
28
29
24
25
30
31
RD
CS
46
47
H_DM2
H_DP2
USB
TRANSCEIVER
WR
ON-THE-GO
CONTROLLER
BUS
INTERFACE
A0
A1
DACK1
DACK2
DREQ1
DREQ2
INT1
49
50
OTG_DM1
OTG_DP1
OTG
TRANSCEIVER
PHILIPS DEVICE
CONTROLLER
INT2
CHARGE
PUMP
55
V
BUS
23
59
60
TEST0
TEST1
TEST2
DC BUFFER
MEMORY
GOODLINK
1, 9, 19, 27,
37, 57
4, 14, 26,
40, 52, 58
51
34
39
45
48
54
53
004aaa044
DGND
AGND
V
D_SUSPEND/
D_WAKEUP
GL
ID
OTGMODE
CP_CAP2 CP_CAP1
CC
Fig 1. Block diagram.
NXP [ NXP ]
