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ISP1362BD 参数 Datasheet PDF下载

ISP1362BD图片预览
型号: ISP1362BD
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片通用串行总线- The-Go的控制器 [Single-chip Universal Serial Bus On-The-Go controller]
分类和应用: 控制器
文件页数/大小: 150 页 / 621 K
品牌: NXP [ NXP ]
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ISP1362  
Single-chip USB OTG controller  
Philips Semiconductors  
7.2 Pin description  
Table 2:  
Symbol[1]  
Pin description  
Pin  
LQFP64 TFBGA64  
Ball  
Type[2] Description  
DGND  
D2  
1
B1  
C2  
-
digital ground  
2
I/O  
bit 2 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
D3  
3
C1  
I/O  
bit 3 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
VCC  
D4  
4
5
D2  
D1  
-
supply voltage (3.3 V); it is recommended to connect a decoupling  
capacitor of 0.01 µF  
I/O  
bit 4 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
D5  
D6  
D7  
6
7
8
E2  
E1  
F2  
I/O  
I/O  
I/O  
bit 5 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
bit 6 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
bit 7 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
digital ground  
DGND  
D8  
9
F1  
-
10  
G2  
I/O  
bit 8 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
D9  
11  
12  
13  
G1  
H2  
H1  
I/O  
I/O  
I/O  
bit 9 of the bidirectional data bus that connects to the internal registers  
and buffer memory of the ISP1362; the bus is in the high-impedance  
state when it is idle  
bidirectional, push-pull input, three-state output  
D10  
D11  
bit 10 of the bidirectional data bus that connects to the internal  
registers and buffer memory of the ISP1362; the bus is in the  
high-impedance state when it is idle  
bidirectional, push-pull input, three-state output  
bit 11 of the bidirectional data bus that connects to the internal  
registers and buffer memory of the ISP1362; the bus is in the  
high-impedance state when it is idle  
bidirectional, push-pull input, three-state output  
9397 750 12337  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 06 January 2004  
8 of 150  
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