ISP1362
Single-chip USB OTG controller
Philips Semiconductors
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller. Data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of the DC in 8237 compatible DMA mode is given in Figure 26.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
MEMR
RAM
D0 to D15
MEMW
DMA
CPU
CONTROLLER
8237
ISP1362
DREQ2
DACK2
DREQ
HRQ
HRQ
HLDA
DACK
HLDA
RD
IOR
WR
IOW
004aaa047
Fig 26. DC in 8327 compatible DMA mode.
The following example shows the steps that occur in a typical DMA transfer:
1. The DC receives a data packet in one of its endpoint buffer memory. The packet
must be transferred to memory address 1234H.
2. The DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
control signals.
6. The 8237 asserts DACK to inform the DC that it will start a DMA transfer.
7. The DC now places the word to be transferred on the data bus lines because its
RD signal was asserted by the 8237.
8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This
latches and stores the word at the desired memory location. It also informs
the DC that the data on the bus lines has been transferred.
9. The DC deasserts the DREQ2 signal to indicate to the 8237 that DMA is no
longer needed. In the Single cycle mode, this is done after each byte or word; in
the Burst mode, following the last transferred byte or word of the DMA cycle.
10. The 8237 deasserts the DACK output indicating that the DC must stop placing
data on the bus.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
56 of 150
NXP [ NXP ]
