ISP1362
Single-chip USB OTG controller
Philips Semiconductors
The following features are supported:
• Single-cycle or burst transfers (up to 16 bytes per cycle)
• Programmable transfer direction (read or write)
• Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet
• Programmable signal levels on pins DREQ2 and DACK2.
13.4.1 Selecting an endpoint for the DMA transfer
The target endpoint for DMA access is selected using bits EPDIX[3:0] of the
DcDMAConfiguration register, as shown in Table 17. The transfer direction (read or
write) is automatically set by the EPDIR bit in the associated ECR, to match the
selected endpoint type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK2 automatically selects the endpoint specified in the
DcDMAConfiguration register, regardless of the current endpoint used for the
I/O mode access.
Table 17: Endpoint selection for DMA transfer
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
1
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2
3
4
5
6
7
8
9
10
11
12
13
14
13.4.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing the DAKOLY bit of the
DcHardwareConfiguration register (see Table 114). The pin functions for this mode
are shown in Table 18.
Table 18: 8237 compatible mode: pin functions
Symbol
DREQ2
DACK2
EOT
Description
I/O
Function
DMA request of DC
DMA acknowledge of DC
end of transfer
read strobe
O
I
DC requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs the DC to put data on the bus
instructs the DC to get data from the bus
I
RD
I
WR
write strobe
I
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
55 of 150
NXP [ NXP ]
