ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
the DC DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1
and DACK1.
When the DMA transfer is terminated, the buffer is also cleared (even if data is not
completely read) and the DMA handler is automatically disabled. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
13.3 Endpoint description
13.3.1 Endpoints with programmable buffer memory size
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the USB host and the
USB device. At design time, each endpoint is assigned a unique number (endpoint
identifier, see Table 14). The combination of the device address (given by the host
during enumeration), the endpoint number, and the transfer direction allows each
endpoint to be uniquely referenced.
The DC has 16 endpoints: endpoint 0 (control IN and OUT) and 14 configurable
endpoints, which can be individually defined as interrupt, bulk or isochronous—IN or
OUT. Each enabled endpoint has an associated buffer memory, which can be
accessed either by using the programmed I/O interface mode or by using the DMA
mode.
13.3.2 Endpoint access
Table 14 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support the DMA mode access. DC buffer
memory DMA access is selected and enabled using bits EPIDX[3:0] and DMAEN of
the DcDMAConfiguration register. A detailed description of the DC DMA operation is
given in Section 13.4.
Table 14: Endpoint access and programmability
Endpoint
identifier
Buffer memory size
(bytes)[1]
Double
buffering
PIO mode
access
DMA mode
access
Endpoint type
0
64 (fixed)
no
yes
no
control OUT[2][3]
control IN[2][3]
programmable
0
64 (fixed)
no
yes
no
1 to 14
programmable
supported
supported
supported
[1] The total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes.
[2] IN: input for the USB host (DC transmits); OUT: output from the USB host (DC receives).
[3] The data flow direction is determined by the EPDIR bit of the DcEndpointConfiguration register.
13.3.3 Endpoint buffer memory size
The size of the buffer memory determines the maximum packet size that the
hardware can support for a given endpoint. Only enabled endpoints are allocated
space in the shared buffer memory storage, disabled endpoints have zero bytes.
Table 15 lists the programmable buffer memory sizes.
The following bits of the DcEndpointConfiguration register (ECR) affect the buffer
memory allocation:
• Endpoint enable bit (FIFOEN)
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
52 of 150
NXP [ NXP ]
