ISP1362
Single-chip USB OTG controller
Philips Semiconductors
1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the
clock signals are routed to all internal circuits of the DC in the ISP1362.
2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the
DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the
DcInterruptEnable register is set.
3. 5 ms after starting the wake-up sequence, the DC in the ISP1362 resumes its
normal functionality (this could be set to 100 µs by setting pin TEST0 to HIGH).
4. In case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB
bus for 10 ms.
5. The application restores itself and other system components to normal operating
mode.
6. After wake-up, the internal registers of the DC in the ISP1362 are read and
write-protected to prevent corruption by inadvertent writing during power-up of
external components. The firmware must send an Unlock Device command to
the DC in the ISP1362 to restore its full functionality.
14. OTG registers
Table 21: OTG Control registers summary
Command (Hex)
Register
Width
References
Functionality
Read
62
Write
E2
OtgControl
16
16
16
16
32
32
Section 14.1 on page 60 OTG Operation registers
Section 14.2 on page 62
67
N/A
E8
OtgStatus
68
OtgInterrupt
OtgInterruptEnable
OtgTimer
Section 14.3 on page 63
69
E9
Section 14.4 on page 66
6A
6C
EA
Section 14.5 on page 67
EC
OtgAltTimer
Section 14.6 on page 68
14.1 OtgControl register (R/W: 62H/E2H)
Code (Hex): 62 — read
Code (Hex): E2 — write
Table 22: OtgControl register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
OTG_SE0_
EN
A_SRP_
DET_EN
A_SEL_
SRP
SEL_HC_
DC
Reset
Access
Bit
-
-
-
-
-
-
-
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
-
5
7
6
4
Symbol
LOC_
PULLDN_
DM
LOC_
A_RDIS_
LOC_
CONN
SEL_CP_ DISCHRG_
CHRG_
VBUS
DRV_
VBUS
PULLDN_ LCON_EN
DP
EXT
VBUS
Reset
1
1
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
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