ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Isochronous endpoints: A DMA transfer to or from an isochronous endpoint can be
terminated by any of the following conditions (bit names refer to the
DcDMAConfiguration register, see Table 118 and Table 119):
• The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
• An End-Of-Packet (EOP) signal is detected
• DMA operation is disabled by clearing bit DMAEN.
Table 20: Recommended EOT usage for isochronous endpoints
EOT condition
OUT endpoint
IN endpoint
DcDMACounter register zero
do not use
preferred
13.5 ISP1362 DC suspend and resume
13.5.1 Suspend conditions
The DC in the ISP1362 detects a USB suspend condition in either of the following
cases:
• Constant idle state is present on the USB bus for 3 ms.
• VBUS is lost.
Bus-powered devices that are suspended must not consume more than 500 µA of
current. This is achieved by shutting down the power to system components or
supplying them with a reduced voltage.
The steps leading the DC to the suspend state are as follows:
1. In the event of no SOF for 3 ms, the DC in the ISP1362 sets bit SUSPND of the
DcInterrupt register. This will generate an interrupt if bit IESUSP of the
DcInterruptEnable register is set.
2. When the firmware detects a suspend condition (through the IESUSP), it must
prepare all system components for the suspend state:
a. All the signals connected to the DC in the ISP1362 must enter appropriate
states to meet the power consumption requirements of the suspend state.
b. All the input pins of the DC in the ISP1362 must have a CMOS logic 0 or
logic 1 level.
3. In the interrupt service routine, the firmware must check the current status of the
USB bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus
has left the suspend mode and the process must be aborted. Otherwise, the next
step can be executed.
4. To meet the suspend current requirements for a bus-powered device, the internal
clocks must be switched off by clearing bit CLKRUN of the
DcHardwareConfiguration register.
5. When the firmware has set and cleared the GOSUSP bit of the DcMode register,
the DC in the ISP1362 enters the suspend state. It sets the
D_SUSPEND/D_WAKEUP pin to HIGH and switches off the internal clocks after
2 ms.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
58 of 150
NXP [ NXP ]
